Lines Matching +full:pcie2 +full:- +full:phy
1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
18 - 8 Ethernet interfaces, supporting combinations of the following:
19 - Up to four 10 Gbps Ethernet MACs
20 - Up to eight 1 Gbps Ethernet MACs
21 - Up to four 2.5 Gbps Ethernet MACs
22 - High-speed peripheral interfaces
23 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
24 - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
25 - Additional peripheral interfaces
26 - Two serial ATA (SATA 2.0) controllers
27 - Two high-speed USB 2.0 controllers with integrated PHY
28 - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
29 - Enhanced serial peripheral interface (eSPI)
30 - Four I2C controllers
31 - Four 2-pin UARTs or two 4-pin UARTs
32 - Integrated Flash Controller supporting NAND and NOR flash
33 - Three eight-channel DMA engines
34 - Support for hardware virtualization and partitioning enforcement
35 - QorIQ Platform's Trust Architecture 2.0
38 -----------------------------------
46 SoC Package: 896-pins 780-pins
49 T2080PCIe-RDB board Overview
50 ----------------------------
51 - SERDES Configuration
52 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
53 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
54 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
55 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
56 - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
57 - SerDes-2 Lane G-H: to SATA1 & SATA2
58 - Ethernet
59 - Two on-board 10M/100M/1G RGMII ethernet ports
60 - Two on-board 10Gbps XFI fiber ports
61 - Two on-board 10Gbps Base-T copper ports
62 - DDR Memory
63 - Supports 72bit 4GB DDR3-LP SODIMM
64 - PCIe
65 - One PCIe x4 gold-finger
66 - One PCIe x4 connector
67 - One PCIe x2 end-point device (C293 Crypto co-processor)
68 - IFC/Local Bus
69 - NOR: 128MB 16-bit NOR Flash
70 - NAND: 1GB 8-bit NAND flash
71 - CPLD: for system controlling with programable header on-board
72 - SATA
73 - Two SATA 2.0 onnectors on-board
74 - USB
75 - Supports two USB 2.0 ports with integrated PHYs
76 - Two type A ports with 5V@1.5A per port.
77 - SDHC
78 - one TF-card connector on-board
79 - SPI
80 - On-board 64MB SPI flash
81 - Other
82 - Two Serial ports
83 - Four I2C ports
87 -----------------
89 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
90 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
98 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
108 -------------------------
110 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
111 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
113 0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB
118 0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
119 0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
121 0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
128 T2080PCIe-RDB Ethernet Port Map
129 -------------------------------
130 Label In Uboot In Linux FMan Address Comments PHY
131 ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
132 ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
133 ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
134 ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
135 ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E)
136 ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E)
139 T2080PCIe-RDB Default DIP-Switch setting
140 ----------------------------------------
146 ------------------------------------------
151 b. program u-boot.bin image to NOR flash
152 => tftp 1000000 u-boot.bin
158 via software: run command 'cpld reset altbank' in U-Boot.
159 via DIP-switch: set SW3[5:7] = '100'
162 via software: run command 'cpld reset' in U-Boot.
163 via DIP-Switch: set SW3[5:7] = '000'
169 b. program u-boot-with-spl-pbl.bin to NAND flash
170 => tftp 1000000 u-boot-with-spl-pbl.bin
179 b. program u-boot-with-spl-pbl.bin to SPI flash
180 => tftp 1000000 u-boot-with-spl-pbl.bin
190 b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
191 => tftp 1000000 u-boot-with-spl-pbl.bin
196 2-stage NAND/SPI/SD boot loader
197 -------------------------------
198 PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
200 and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
201 Finally SPL transers control to U-Boot for futher booting.
204 - Executes within 256K
205 - No relocation required
208 -------------------------------------------------
210 -------------------------------------------------
212 -------------------------------------------------
214 -------------------------------------------------
216 -------------------------------------------------
218 -------------------------------------------------
220 -------------------------------------------------
221 |U-Boot SPL | 0xFFFD8000 (160KB) |
222 -------------------------------------------------
225 --------------------------------------------------------------
227 0x000000 0x0FFFFF U-Boot img 1MB (2 blocks)
228 0x100000 0x17FFFF U-Boot env 512KB (1 block)
234 ----------------------------------------------------
236 0x008 2048 U-Boot img 1MB
237 0x800 0016 U-Boot env 8KB
243 ----------------------------------------------------
245 0x000000 0x0FFFFF U-Boot img 1MB
246 0x100000 0x101FFF U-Boot env 8KB
251 How to update the ucode of Cortina CS4315/CS4340 10G PHY
252 --------------------------------------------------------
253 => tftp 1000000 CS4315-CS4340-PHY-ucode.txt
258 -----------------------------------------
263 For more details, please refer to T2080PCIe-RDB User Guide and access