Lines Matching +full:target +full:- +full:12 +full:v +full:- +full:supply
2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
21 - CoreNet coherency manager supporting coherent and noncoherent transactions
23 - 150 Gbps coherent read bandwidth
24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
25 - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
26 - Packet parsing, classification, and distribution
27 - Queue management for scheduling, packet sequencing, and congestion management
28 - Cryptography Acceleration (SEC 5.x)
29 - IEEE 1588 support
30 - Hardware buffer management for buffer allocation and deallocation
31 - MACSEC on DPAA-based Ethernet ports
32 - Ethernet interfaces
33 - Four 1 Gbps Ethernet controllers
34 - Parallel Ethernet interfaces
35 - Two RGMII interfaces
36 - High speed peripheral interfaces
37 - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
38 - One SATA controller supporting 1.5 and 3.0 Gb/s operation
39 - One QSGMII interface
40 - Four SGMII interface supporting 1000 Mbps
41 - Three SGMII interfaces supporting up to 2500 Mbps
42 - 10GbE XFI or 10Base-KR interface
43 - Additional peripheral interfaces
44 - Two USB 2.0 controllers with integrated PHY
45 - SD/eSDHC/eMMC
46 - eSPI controller
47 - Four I2C controllers
48 - Four UARTs
49 - Four GPIO controllers
50 - Integrated flash controller (IFC)
51 - LCD interface (DIU) with 12 bit dual data rate
52 - Multicore programmable interrupt controller (PIC)
53 - Two 8-channel DMA engines
54 - Single source clocking implementation
55 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
56 - QUICC Engine block
57 - 32-bit RISC controller for flexible support of the communications peripherals
58 - Serial DMA channel for receive and transmit on all serial channels
59 - Two universal communication controllers, supporting TDM, HDLC, and UART
62 ------------------
71 DDR: 64-bit 32-bit
72 IFC: 32-bit 28-bit
76 -----------------------
77 - SERDES Connections
79 - PCI Express: supports Gen 1 and Gen 2
80 - SGMII 1G and SGMII 2.5G
81 - QSGMII
82 - XFI
83 - SATA 2.0
84 - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
85 - Aurora debug with dedicated connectors.
86 - DDR Controller
87 - Supports up to 1600 MTPS data-rate.
88 - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
89 - Supports Single-, dual- or quad-rank DIMMs
90 - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
91 - IFC/Local Bus
92 - NAND Flash: 8-bit, async, up to 2GB
93 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
94 - NOR devices support 8 virtual banks
95 - Socketed to allow alternate devices
96 - GASIC: Simple (minimal) target within QIXIS FPGA
97 - PromJET rapid memory download support
98 - IFC Debug/Development card
99 - Ethernet
100 - Two on-board RGMII 10M/100M/1G ethernet ports.
101 - One QSGMII interface
102 - Four SGMII interface supporting 1Gbps
103 - Three SGMII interfaces supporting 2.5Gbps
104 - one 10Gbps XFI or 10Base-KR interface
105 - QIXIS System Logic FPGA
106 - Manages system power and reset sequencing.
107 - Manages the configurations of DUT, board, and clock for dynamic shmoo.
108 - Collects V-I-T data in background for code/power profiling.
109 - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
110 - General fault monitoring and logging.
111 …- Powered from ATX 'standby' power supply that allows continuous operation while rest of the syste…
112 - Clocks
113 - System and DDR clock (SYSCLK, DDRCLK).
114 - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
115 - Software programmable in 1 MHz increments from 1-200 MHz.
116 - SERDES clocks
117 - Provides clocks to SerDes blocks and slots.
118 - 100 MHz, 125 MHz and 156.25 MHz options.
119 - Spread-spectrum option for 100 MHz.
120 - Power Supplies
121 - Dedicated PMBus regulator for VDD and VDDC.
122 - Adjustable from 0.7V to 1.3V at 35A
123 - VDD can be disabled independanty from VDDC for “deep sleep”.
124 - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
125 - VTT/MVREF automatically track operating voltage.
126 - Dedicated 2.5V VPP supply.
127 - Dedicated regulators/filters for AVDD supplies.
128 - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
129 - Video
130 - DIU supports video up to 1280x1024x32 bpp.
131 - Chrontel CH7201 for HDMI connection.
132 - TI DS90C387R for direct LCD connection.
133 - Raw (not encoded) video connector for testing or other encoders.
134 - USB
135 - Supports two USB 2.0 ports with integrated PHYs.
136 - Two type A ports with 5V@1.5A per port.
137 - Second port can be converted to OTG mini-AB.
138 - SDHC
140 - upport for optional clock feedback paths.
141 - Support for optional high-speed voltage translation direction controls.
142 - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
143 - Support for eMMC memory devices.
144 - SPI
145 -On-board support of 3 different devices and sizes.
146 - Other IO
147 - Two Serial ports
148 - ProfiBus port
149 - Four I2C ports
153 ----------------------
155 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
156 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
163 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
173 --------------------------
175 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
176 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
183 0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
184 0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
193 SerDes clock vs DIP-switch settings
194 -----------------------------------
202 ----------------------
211 ------------------------------------------
217 b. program u-boot.bin image to NOR flash
218 => tftp 1000000 u-boot.bin
224 via software: run command 'qixis_reset altbank' in U-Boot.
225 via DIP-switch: set SW6[1:4] = '0100'
228 via software: run command 'qixis_reset' in U-Boot.
229 via DIP-Switch: set SW6[1:4] = '0000'
235 b. program u-boot-with-spl-pbl.bin to NAND flash
236 => tftp 1000000 u-boot-with-spl-pbl.bin
245 b. program u-boot-with-spl-pbl.bin to SPI flash
246 => tftp 1000000 u-boot-with-spl-pbl.bin
256 b. program u-boot-with-spl-pbl.bin to SD/MMC card
257 => tftp 1000000 u-boot-with-spl-pbl.bin
264 DIU/QE-TDM/SDXC settings
265 -------------------
272 2-stage NAND/SPI/SD boot loader
273 -------------------------------
274 PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
276 and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
277 Finally SPL transers control to U-Boot for futher booting.
280 - Executes within 256K
281 - No relocation required
284 -------------------------------------------------
286 -------------------------------------------------
288 -------------------------------------------------
290 -------------------------------------------------
292 -------------------------------------------------
294 -------------------------------------------------
296 -------------------------------------------------
297 |U-Boot SPL | 0xFFFD8000 (160KB) |
298 -------------------------------------------------
301 -------------------------------------------------------------
303 0x000000 0x0FFFFF U-Boot 1MB
304 0x100000 0x15FFFF U-Boot env 8KB
310 ----------------------------------------------------
312 0x008 2048 U-Boot img 1MB
313 0x800 0016 U-Boot env 8KB
319 ----------------------------------------------------
321 0x000000 0x0FFFFF U-Boot img 1MB
322 0x100000 0x101FFF U-Boot env 8KB