Lines Matching +full:0 +full:x50000000

10 	/* TLB 0 - for temp stack in cache */
11 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
12 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
13 		      0, 0, BOOKE_PAGESZ_4K, 0),
14 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
16 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 		      0, 0, BOOKE_PAGESZ_4K, 0),
18 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
20 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 		      0, 0, BOOKE_PAGESZ_4K, 0),
22 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
24 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 		      0, 0, BOOKE_PAGESZ_4K, 0),
29 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31 		      0, 0, BOOKE_PAGESZ_4K, 1),
36 		      0, 1, BOOKE_PAGESZ_4M, 1),
42 		      0, 2, BOOKE_PAGESZ_256M, 1),
47 		      0, 3, BOOKE_PAGESZ_1G, 1),
50 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
51 		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
53 		      0, 4, BOOKE_PAGESZ_256M, 1),
55 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
56 		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
58 		      0, 5, BOOKE_PAGESZ_256M, 1),
63 		      0, 6, BOOKE_PAGESZ_256K, 1),
67 		      MAS3_SW|MAS3_SR, 0,
68 		      0, 7, BOOKE_PAGESZ_1M, 1),
69 	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
70 		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
72 		      0, 8, BOOKE_PAGESZ_1M, 1),
75 		      0, 9, BOOKE_PAGESZ_1M, 1),
76 	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
77 		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
79 		      0, 10, BOOKE_PAGESZ_1M, 1),
83 		      0, 11, BOOKE_PAGESZ_16K, 1),
89 		      0, 12, BOOKE_PAGESZ_256M, 1),
91 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
92 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
94 		      0, 13, BOOKE_PAGESZ_256M, 1),