Lines Matching +full:0 +full:x50000000

12 	/* TLB 0 - for temp stack in cache */
13 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
14 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
15 		      0, 0, BOOKE_PAGESZ_4K, 0),
16 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 		      0, 0, BOOKE_PAGESZ_4K, 0),
20 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
22 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 		      0, 0, BOOKE_PAGESZ_4K, 0),
24 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
26 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
27 		      0, 0, BOOKE_PAGESZ_4K, 0),
31 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
33 		      0, 0, BOOKE_PAGESZ_4K, 1),
38 		      0, 1, BOOKE_PAGESZ_1M, 1),
45 		      0, 2, BOOKE_PAGESZ_256M, 1),
50 		      0, 3, BOOKE_PAGESZ_1G, 1),
53 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
54 		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
56 		      0, 4, BOOKE_PAGESZ_256M, 1),
58 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
59 		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
61 		      0, 5, BOOKE_PAGESZ_256M, 1),
66 		      0, 6, BOOKE_PAGESZ_256K, 1),
71 		      0, 7, BOOKE_PAGESZ_4K, 1),
78 		      0, 8, BOOKE_PAGESZ_1G, 1),
80 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
81 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
83 		      0, 9, BOOKE_PAGESZ_1G, 1),
90 		      0, 10, BOOKE_PAGESZ_16K, 1),
97 		      0, 11, BOOKE_PAGESZ_256K, 1)