1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/mx6-ddr.h>
13 #include <asm/arch/mx6-pins.h>
64 	/* SDCKE[0:1]: 100k pull-up */
67 	/* SDBA2: pull-up disabled */
69 	/* SDODT[0:1]: 100k pull-up, 40 ohm */
104 	/* DATA[00:63]: Differential input, 40 ohm */
123 	/* SDCKE[0:1]: 100k pull-up */
126 	/* SDBA2: pull-up disabled */
128 	/* SDODT[0:1]: 100k pull-up, 40 ohm */
164 	/* DATA[00:63]: Differential input, 40 ohm */
208 	/* width of data bus:0=16,1=32,2=64 */
230 	.sde_to_rst = 0x10,	/* JEDEC value for LPDDR2 - 200us */
231 	.pd_fast_exit = 0,	/* immaterial for calibration */
236 	.pd_fast_exit = 0,	/* immaterial for calibration */
244 /* Micron MT41K512M16TNA-125 */
258 /* Micron MT41K128M16JT-125 */
338 	writel(0x00C03F3F, &ccm->CCGR0);  in ccgr_init()
339 	writel(0x0030FC03, &ccm->CCGR1);  in ccgr_init()
340 	writel(0x0FFFC000, &ccm->CCGR2);  in ccgr_init()
341 	writel(0x3FF00000, &ccm->CCGR3);  in ccgr_init()
342 	writel(0x00FFF300, &ccm->CCGR4);  in ccgr_init()
343 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
344 	writel(0x000003FF, &ccm->CCGR6);  in ccgr_init()
349 	printf(".p0_mpdgctrl0\t= 0x%08X\n", calib->p0_mpdgctrl0);  in display_calibration()
350 	printf(".p0_mpdgctrl1\t= 0x%08X\n", calib->p0_mpdgctrl1);  in display_calibration()
351 	printf(".p0_mprddlctl\t= 0x%08X\n", calib->p0_mprddlctl);  in display_calibration()
352 	printf(".p0_mpwrdlctl\t= 0x%08X\n", calib->p0_mpwrdlctl);  in display_calibration()
353 	printf(".p0_mpwldectrl0\t= 0x%08X\n", calib->p0_mpwldectrl0);  in display_calibration()
354 	printf(".p0_mpwldectrl1\t= 0x%08X\n", calib->p0_mpwldectrl1);  in display_calibration()
356 		printf(".p1_mpdgctrl0\t= 0x%08X\n", calib->p1_mpdgctrl0);  in display_calibration()
357 		printf(".p1_mpdgctrl1\t= 0x%08X\n", calib->p1_mpdgctrl1);  in display_calibration()
358 		printf(".p1_mprddlctl\t= 0x%08X\n", calib->p1_mprddlctl);  in display_calibration()
359 		printf(".p1_mpwrdlctl\t= 0x%08X\n", calib->p1_mpwrdlctl);  in display_calibration()
360 		printf(".p1_mpwldectrl0\t= 0x%08X\n", calib->p1_mpwldectrl0);  in display_calibration()
361 		printf(".p1_mpwldectrl1\t= 0x%08X\n", calib->p1_mpwldectrl1);  in display_calibration()
364 	printf("DATA 4 MX6_MMDC_P0_MPDGCTRL0\t= 0x%08X\n", calib->p0_mpdgctrl0);  in display_calibration()
365 	printf("DATA 4 MX6_MMDC_P0_MPDGCTRL1\t= 0x%08X\n", calib->p0_mpdgctrl1);  in display_calibration()
366 	printf("DATA 4 MX6_MMDC_P0_MPRDDLCTL\t= 0x%08X\n", calib->p0_mprddlctl);  in display_calibration()
367 	printf("DATA 4 MX6_MMDC_P0_MPWRDLCTL\t= 0x%08X\n", calib->p0_mpwrdlctl);  in display_calibration()
368 	printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL0\t= 0x%08X\n",  in display_calibration()
369 	       calib->p0_mpwldectrl0);  in display_calibration()
370 	printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL1\t= 0x%08X\n",  in display_calibration()
371 	       calib->p0_mpwldectrl1);  in display_calibration()
373 		printf("DATA 4 MX6_MMDC_P1_MPDGCTRL0\t= 0x%08X\n",  in display_calibration()
374 		       calib->p1_mpdgctrl0);  in display_calibration()
375 		printf("DATA 4 MX6_MMDC_P1_MPDGCTRL1\t= 0x%08X\n",  in display_calibration()
376 		       calib->p1_mpdgctrl1);  in display_calibration()
377 		printf("DATA 4 MX6_MMDC_P1_MPRDDLCTL\t= 0x%08X\n",  in display_calibration()
378 		       calib->p1_mprddlctl);  in display_calibration()
379 		printf("DATA 4 MX6_MMDC_P1_MPWRDLCTL\t= 0x%08X\n",  in display_calibration()
380 		       calib->p1_mpwrdlctl);  in display_calibration()
381 		printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL0\t= 0x%08X\n",  in display_calibration()
382 		       calib->p1_mpwldectrl0);  in display_calibration()
383 		printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL1\t= 0x%08X\n",  in display_calibration()
384 		       calib->p1_mpwldectrl1);  in display_calibration()
391  * - we have a stack and a place to store GD, both in SRAM
392  * - no variable global data is available
397 	struct mx6_mmdc_calibration calibration = {0};  in board_init_f()  local
401 	/* write leveling calibration defaults */  in board_init_f()
402 	calibration.p0_mpwrdlctl = 0x40404040;  in board_init_f()
403 	calibration.p1_mpwrdlctl = 0x40404040;  in board_init_f()
415 	/* UART clocks enabled and gd valid - init serial console */  in board_init_f()
423 			printf("cpu type 0x%x doesn't support 64-bit bus\n",  in board_init_f()
440 	mx6_dram_cfg(&sysinfo, &calibration, &ddrtype);  in board_init_f()
444 		printf("error %d from write level calibration\n", errs);  in board_init_f()
448 			printf("error %d from dqs calibration\n", errs);  in board_init_f()
451 			mmdc_read_calibration(&sysinfo, &calibration);  in board_init_f()
452 			display_calibration(&calibration);  in board_init_f()