Lines Matching +full:5 +full:k
24 SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
41 SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
50 SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX
60 SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined
65 SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
74 SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
83 It is possible to use either half to boot using U-Boot. Switch 5 bit 2
92 use switch 5, bit 2 to alternate between the halves. Note: The booting
126 0xffdf_0000 0xffdf_7fff PIXIS 8K
127 0xffdf_8000 0xffdf_ffff CF 8K
128 0xf840_0000 0xf840_3fff Stack space 32K
129 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
130 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
147 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
148 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
149 0x0_f840_0000 0xf_f840_3fff Stack space 32K
150 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K
151 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K
154 5. pixis_reset command