34 	gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */  in board_early_init_f()
36 	return 0;  in board_early_init_f()
46 	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);  in misc_init_r()
48 	/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/  in misc_init_r()
50 	if(version >= 0x07) {  in misc_init_r()
52 		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);  in misc_init_r()
56 	 *  Enable the TFP410 Encoder (I2C address 0x38)  in misc_init_r()
59 	tmp_val = 0xBF;  in misc_init_r()
60 	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));  in misc_init_r()
62 	tmp_val = 0;  in misc_init_r()
63 	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));  in misc_init_r()
64 	debug("DVI Encoder Read: 0x%02x\n", tmp_val);  in misc_init_r()
66 	tmp_val = 0x10;  in misc_init_r()
67 	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));  in misc_init_r()
69 	tmp_val = 0;  in misc_init_r()
70 	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));  in misc_init_r()
71 	debug("DVI Encoder Read: 0x%02x\n", tmp_val);  in misc_init_r()
73 	return 0;  in misc_init_r()
82 	printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "  in checkboard()
83 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",  in checkboard()
93 	switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {  in checkboard()
94 	case 0:  in checkboard()
97 	case 0x40:  in checkboard()
100 	case 0x80:  in checkboard()
103 	case 0xC0:  in checkboard()
108 	mcm->abcr |= 0x00010000; /* 0 */  in checkboard()
109 	mcm->hpmr3 = 0x80000008; /* 4c */  in checkboard()
110 	mcm->hpmr0 = 0;  in checkboard()
111 	mcm->hpmr1 = 0;  in checkboard()
112 	mcm->hpmr2 = 0;  in checkboard()
113 	mcm->hpmr4 = 0;  in checkboard()
114 	mcm->hpmr5 = 0;  in checkboard()
116 	return 0;  in checkboard()
122 	phys_size_t dram_size = 0;  in dram_init()
135 	return 0;  in dram_init()
151 	ddr->cs0_bnds = 0x0000001f;  in fixed_sdram()
152 	ddr->cs0_config = 0x80010202;  in fixed_sdram()
154 	ddr->timing_cfg_3 = 0x00000000;  in fixed_sdram()
155 	ddr->timing_cfg_0 = 0x00260802;  in fixed_sdram()
156 	ddr->timing_cfg_1 = 0x3935d322;  in fixed_sdram()
157 	ddr->timing_cfg_2 = 0x14904cc8;  in fixed_sdram()
158 	ddr->sdram_mode = 0x00480432;  in fixed_sdram()
159 	ddr->sdram_mode_2 = 0x00000000;  in fixed_sdram()
160 	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */  in fixed_sdram()
161 	ddr->sdram_data_init = 0xDEADBEEF;  in fixed_sdram()
162 	ddr->sdram_clk_cntl = 0x03800000;  in fixed_sdram()
163 	ddr->sdram_cfg_2 = 0x04400010;  in fixed_sdram()
166 	ddr->err_int_en = 0x0000000d;  in fixed_sdram()
167 	ddr->err_disable = 0x00000000;  in fixed_sdram()
168 	ddr->err_sbe = 0x00010000;  in fixed_sdram()
174 	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/  in fixed_sdram()
184 	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)  in fixed_sdram()
230 	first_free_busno = fsl_pcie_init_board(0);  in pci_init_board()
269 	return 0;  in ft_board_setup()
282 	ulong val = 0;  in get_board_sys_clk()
286 	i &= 0x07;  in get_board_sys_clk()
289 	case 0:  in get_board_sys_clk()
327 	out_8(pixis_base + PIXIS_RST, 0);  in board_reset()