Lines Matching +full:0 +full:x50000000

13 	/* TLB 0 - for temp stack in cache */
14 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 		      0, 0, BOOKE_PAGESZ_4K, 0),
17 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 		      0, 0, BOOKE_PAGESZ_4K, 0),
20 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 		      0, 0, BOOKE_PAGESZ_4K, 0),
23 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
24 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 		      0, 0, BOOKE_PAGESZ_4K, 0),
29 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31 		      0, 0, BOOKE_PAGESZ_4K, 1),
36 		      0, 1, BOOKE_PAGESZ_1M, 1),
42 		      0, 2, BOOKE_PAGESZ_256M, 1),
48 		      0, 3, BOOKE_PAGESZ_1G, 1),
51 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
53 		      0, 4, BOOKE_PAGESZ_256M, 1),
55 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
57 		      0, 5, BOOKE_PAGESZ_256M, 1),
62 		      0, 6, BOOKE_PAGESZ_256K, 1),
68 		      0, 7, BOOKE_PAGESZ_1M, 1),
72 		      0, 8, BOOKE_PAGESZ_4K, 1),
79 			0, 9, BOOKE_PAGESZ_256K, 1),
80 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
81 			CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
83 			0, 10, BOOKE_PAGESZ_256K, 1),