Lines Matching full:2
26 {4, 10, 1, 0, 2}, /* TxD0 */
27 {4, 9, 1, 0, 2}, /* TxD1 */
28 {4, 8, 1, 0, 2}, /* TxD2 */
29 {4, 7, 1, 0, 2}, /* TxD3 */
30 {4, 23, 1, 0, 2}, /* TxD4 */
31 {4, 22, 1, 0, 2}, /* TxD5 */
32 {4, 21, 1, 0, 2}, /* TxD6 */
33 {4, 20, 1, 0, 2}, /* TxD7 */
34 {4, 15, 2, 0, 2}, /* RxD0 */
35 {4, 14, 2, 0, 2}, /* RxD1 */
36 {4, 13, 2, 0, 2}, /* RxD2 */
37 {4, 12, 2, 0, 2}, /* RxD3 */
38 {4, 29, 2, 0, 2}, /* RxD4 */
39 {4, 28, 2, 0, 2}, /* RxD5 */
40 {4, 27, 2, 0, 2}, /* RxD6 */
41 {4, 26, 2, 0, 2}, /* RxD7 */
42 {4, 11, 1, 0, 2}, /* TX_EN */
43 {4, 24, 1, 0, 2}, /* TX_ER */
44 {4, 16, 2, 0, 2}, /* RX_DV */
45 {4, 30, 2, 0, 2}, /* RX_ER */
46 {4, 17, 2, 0, 2}, /* RX_CLK */
47 {4, 19, 1, 0, 2}, /* GTX_CLK */
48 {1, 31, 2, 0, 3}, /* GTX125 */
51 {5, 10, 1, 0, 2}, /* TxD0 */
52 {5, 9, 1, 0, 2}, /* TxD1 */
53 {5, 8, 1, 0, 2}, /* TxD2 */
54 {5, 7, 1, 0, 2}, /* TxD3 */
55 {5, 23, 1, 0, 2}, /* TxD4 */
56 {5, 22, 1, 0, 2}, /* TxD5 */
57 {5, 21, 1, 0, 2}, /* TxD6 */
58 {5, 20, 1, 0, 2}, /* TxD7 */
59 {5, 15, 2, 0, 2}, /* RxD0 */
60 {5, 14, 2, 0, 2}, /* RxD1 */
61 {5, 13, 2, 0, 2}, /* RxD2 */
62 {5, 12, 2, 0, 2}, /* RxD3 */
63 {5, 29, 2, 0, 2}, /* RxD4 */
64 {5, 28, 2, 0, 2}, /* RxD5 */
65 {5, 27, 2, 0, 3}, /* RxD6 */
66 {5, 26, 2, 0, 2}, /* RxD7 */
67 {5, 11, 1, 0, 2}, /* TX_EN */
68 {5, 24, 1, 0, 2}, /* TX_ER */
69 {5, 16, 2, 0, 2}, /* RX_DV */
70 {5, 30, 2, 0, 2}, /* RX_ER */
71 {5, 17, 2, 0, 2}, /* RX_CLK */
72 {5, 19, 1, 0, 2}, /* GTX_CLK */
73 {1, 31, 2, 0, 3}, /* GTX125 */
74 {4, 6, 3, 0, 2}, /* MDIO */
75 {4, 5, 1, 0, 2}, /* MDC */
78 {2, 0, 1, 0, 2}, /* UART_SOUT1 */
79 {2, 1, 1, 0, 2}, /* UART_RTS1 */
80 {2, 2, 2, 0, 2}, /* UART_CTS1 */
81 {2, 3, 2, 0, 2}, /* UART_SIN1 */
136 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; in local_bus_init()
171 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); in lbc_sdram_init()
172 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); in lbc_sdram_init()
257 /*switch temporarily to I2C bus #2 */ in pib_init()