1 // SPDX-License-Identifier: GPL-2.0+
26  *  fixed sdram init -- doesn't use serial presence detect.
30 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;  in fixed_sdram()  local
35 	im->sysconf.ddrlaw[0].ar =  in fixed_sdram()
36 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);  in fixed_sdram()
37 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;  in fixed_sdram()
42 	im->ddr.csbnds[0].csbnds =  in fixed_sdram()
44 		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>  in fixed_sdram()
46 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;  in fixed_sdram()
49 	im->ddr.cs_config[1] = 0;  in fixed_sdram()
50 	im->ddr.cs_config[2] = 0;  in fixed_sdram()
51 	im->ddr.cs_config[3] = 0;  in fixed_sdram()
53 	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);  in fixed_sdram()
54 	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);  in fixed_sdram()
56 	debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);  in fixed_sdram()
57 	debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);  in fixed_sdram()
59 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;  in fixed_sdram()
60 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */  in fixed_sdram()
61 	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;  in fixed_sdram()
62 	im->ddr.sdram_mode =  in fixed_sdram()
64 	im->ddr.sdram_interval =  in fixed_sdram()
67 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;  in fixed_sdram()
71 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;  in fixed_sdram()
73 	debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);  in fixed_sdram()
74 	debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);  in fixed_sdram()
75 	debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);  in fixed_sdram()
76 	debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);  in fixed_sdram()
77 	debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);  in fixed_sdram()
122 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;  in dram_init()  local
125 	volatile ddr83xx_t *ddr = &im->ddr;  in dram_init()
128 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)  in dram_init()
129 		return -ENXIO;  in dram_init()
131 	/* DDR SDRAM - Main SODIMM */  in dram_init()
132 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;  in dram_init()
140 	if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)  in dram_init()
148 	gd->ram_size = msize * 1024 * 1024;  in dram_init()
156 	puts("Board: Freescale MPC8349E-mITX\n");  in checkboard()
158 	puts("Board: Freescale MPC8349E-mITX-GP\n");  in checkboard()
165  * Implement a work-around for a hardware problem with compact
177 	   means it is 0 when the IRQ is not active.  This makes the wire-AND  in misc_init_f()
186 	   unlike U-Boot, Linux uses the IRQ, so this code is necessary if we  in misc_init_f()
187 	   don't enable compact flash for U-Boot.  in misc_init_f()
222 	immap->im_lbc.mamr = 0x08404440;  in misc_init_f()
233  * Miscellaneous late-boot configurations
238  * The MPC8349E-mITX can be configured to load the HRCW from
317 		/* Work-around for MPC8349E-mITX bug #13601.  in misc_init_r()
322 		/* Make sure status register bits 6-2 are zero */  in misc_init_r()
352 		/* Work-around for MPC8349E-mITX bug #13330.  in misc_init_r()