35 	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
43 	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
54 	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
62 	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
76 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;  in dram_init()  local
79 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)  in dram_init()
80 		return -ENXIO;  in dram_init()
82 	/* DDR SDRAM - Main SODIMM */  in dram_init()
83 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;  in dram_init()
87 	/* set total bus SDRAM size(bytes)  -- DDR */  in dram_init()
88 	gd->ram_size = msize * 1024 * 1024;  in dram_init()
94  *  fixed sdram init -- doesn't use serial presence detect.
98 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;  in fixed_sdram()  local
107 			return -1;  in fixed_sdram()
110 	im->sysconf.ddrlaw[0].ar =  in fixed_sdram()
111 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);  in fixed_sdram()
112 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;  in fixed_sdram()
113 	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;  in fixed_sdram()
114 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;  in fixed_sdram()
115 	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;  in fixed_sdram()
116 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;  in fixed_sdram()
117 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;  in fixed_sdram()
118 	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;  in fixed_sdram()
119 	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;  in fixed_sdram()
120 	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;  in fixed_sdram()
121 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;  in fixed_sdram()
122 	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;  in fixed_sdram()
123 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;  in fixed_sdram()
127 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;  in fixed_sdram()
162 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;  in pci_init_board()
163 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;  in pci_init_board()
167 	clk->occr |= 0xe0000000;  in pci_init_board()