1 // SPDX-License-Identifier: GPL-2.0+
26 	if (!pdimm->n_ranks)  in fsl_ddr_board_options()
33 	if (popts->registered_dimm_en)  in fsl_ddr_board_options()
43 	while (pbsp->datarate_mhz_high) {  in fsl_ddr_board_options()
44 		if (pbsp->n_ranks == pdimm->n_ranks &&  in fsl_ddr_board_options()
45 		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {  in fsl_ddr_board_options()
46 			if (ddr_freq <= pbsp->datarate_mhz_high) {  in fsl_ddr_board_options()
47 				popts->clk_adjust = pbsp->clk_adjust;  in fsl_ddr_board_options()
48 				popts->wrlvl_start = pbsp->wrlvl_start;  in fsl_ddr_board_options()
49 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;  in fsl_ddr_board_options()
50 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;  in fsl_ddr_board_options()
61 			ddr_freq, pbsp_highest->datarate_mhz_high);  in fsl_ddr_board_options()
62 		popts->clk_adjust = pbsp_highest->clk_adjust;  in fsl_ddr_board_options()
63 		popts->wrlvl_start = pbsp_highest->wrlvl_start;  in fsl_ddr_board_options()
64 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;  in fsl_ddr_board_options()
65 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;  in fsl_ddr_board_options()
72 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,  in fsl_ddr_board_options()
73 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,  in fsl_ddr_board_options()
74 		pbsp->wrlvl_ctl_3);  in fsl_ddr_board_options()
78 		popts->data_bus_width = 1;  in fsl_ddr_board_options()
79 		popts->otf_burst_chop_en = 0;  in fsl_ddr_board_options()
80 		popts->burst_length = DDR_BL8;  in fsl_ddr_board_options()
81 		popts->bstopre = 0;	/* enable auto precharge */  in fsl_ddr_board_options()
85 	 * Factors to consider for half-strength driver enable:  in fsl_ddr_board_options()
86 	 *	- number of DIMMs installed  in fsl_ddr_board_options()
88 	popts->half_strength_driver_enable = 1;  in fsl_ddr_board_options()
92 	popts->wrlvl_override = 1;  in fsl_ddr_board_options()
93 	popts->wrlvl_sample = 0xf;  in fsl_ddr_board_options()
98 	popts->rtt_override = 0;  in fsl_ddr_board_options()
101 	popts->zq_en = 1;  in fsl_ddr_board_options()
104 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);  in fsl_ddr_board_options()
105 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |  in fsl_ddr_board_options()
106 			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */  in fsl_ddr_board_options()
109 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);  in fsl_ddr_board_options()
110 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);  in fsl_ddr_board_options()
154 		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));  in fsl_ddr_get_dimm_params()
155 		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);  in fsl_ddr_get_dimm_params()
167 	gd->ram_size = fsl_ddr_sdram();  in fsl_initdram()