1 // SPDX-License-Identifier: GPL-2.0+
28 	if (!pdimm->n_ranks)  in fsl_ddr_board_options()
37 	while (pbsp->datarate_mhz_high) {  in fsl_ddr_board_options()
38 		if (pbsp->n_ranks == pdimm->n_ranks) {  in fsl_ddr_board_options()
39 			if (ddr_freq <= pbsp->datarate_mhz_high) {  in fsl_ddr_board_options()
40 				popts->clk_adjust = pbsp->clk_adjust;  in fsl_ddr_board_options()
41 				popts->wrlvl_start = pbsp->wrlvl_start;  in fsl_ddr_board_options()
42 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;  in fsl_ddr_board_options()
43 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;  in fsl_ddr_board_options()
44 				popts->cpo_override = pbsp->cpo_override;  in fsl_ddr_board_options()
45 				popts->write_data_delay =  in fsl_ddr_board_options()
46 					pbsp->write_data_delay;  in fsl_ddr_board_options()
58 		       pbsp_highest->datarate_mhz_high);  in fsl_ddr_board_options()
59 		popts->clk_adjust = pbsp_highest->clk_adjust;  in fsl_ddr_board_options()
60 		popts->wrlvl_start = pbsp_highest->wrlvl_start;  in fsl_ddr_board_options()
61 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;  in fsl_ddr_board_options()
62 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;  in fsl_ddr_board_options()
68 	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);  in fsl_ddr_board_options()
71 	popts->data_bus_width = 1;  in fsl_ddr_board_options()
72 	popts->otf_burst_chop_en = 0;  in fsl_ddr_board_options()
73 	popts->burst_length = DDR_BL8;  in fsl_ddr_board_options()
76 	 * Factors to consider for half-strength driver enable:  in fsl_ddr_board_options()
77 	 *	- number of DIMMs installed  in fsl_ddr_board_options()
79 	popts->half_strength_driver_enable = 1;  in fsl_ddr_board_options()
83 	popts->wrlvl_override = 1;  in fsl_ddr_board_options()
84 	popts->wrlvl_sample = 0xf;  in fsl_ddr_board_options()
89 	popts->rtt_override = 0;  in fsl_ddr_board_options()
92 	popts->zq_en = 1;  in fsl_ddr_board_options()
94 	/* optimize cpo for erratum A-009942 */  in fsl_ddr_board_options()
95 	popts->cpo_sample = 0x46;  in fsl_ddr_board_options()
97 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);  in fsl_ddr_board_options()
98 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |  in fsl_ddr_board_options()
99 			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */  in fsl_ddr_board_options()
102 /* DDR model number: MT40A512M8HX-093E */
165 		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));  in fsl_ddr_get_dimm_params()
166 		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);  in fsl_ddr_get_dimm_params()
211 	gd->ram_size = tfa_get_dram_size();  in fsl_initdram()
212 	if (!gd->ram_size)  in fsl_initdram()
214 		gd->ram_size = fsl_ddr_sdram_size();  in fsl_initdram()
216 		gd->ram_size = 0x80000000;  in fsl_initdram()
237 	gd->ram_size = 0x80000000;  in fsl_initdram()
248 	gd->ram_size = dram_size;  in fsl_initdram()