Lines Matching +full:feedback +full:- +full:pin
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3 The LS1043A Development System (QDS) is a high-performance computing,
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11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
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16 - SERDES Connections, 4 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
19 - QSGMII
20 - SATA 3.0
21 - XFI
22 - DDR Controller
23 - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
24 -IFC/Local Bus
25 - One in-socket 128 MB NOR flash 16-bit data bus
26 - One 512 MB NAND flash with ECC support
27 - PromJet Port
28 - FPGA connection
29 - USB 3.0
30 - Three high speed USB 3.0 ports
31 - First USB 3.0 port configured as Host with Type-A connector
32 - The other two USB 3.0 ports configured as OTG with micro-AB connector
33 - SDHC port connects directly to an adapter card slot, featuring:
34 - Optional clock feedback paths, and optional high-speed voltage translation assistance
35 - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
36 - eMMC memory devices
37 - DSPI: Onboard support for three SPI flash memory devices
38 - 4 I2C controllers
39 - One SATA onboard connectors
40 - UART
41 - Two 4-pin serial ports at up to 115.2 Kbit/s
42 - Two DB9 D-Type connectors supporting one Serial port each
43 - ARM JTAG support
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53 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
54 0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
55 0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
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