9 #define DPM_WP 0x96
10 #define WRP_OPCODE 0x01
11 #define WRM_OPCODE 0x02
12 #define RRP_OPCODE 0x11
14 #define DPM_SUCCESS 0x01
15 #define DPM_EXEC_FAIL 0x00
78 	0,	/* reserved */
87 	ret[0] = RRP_OPCODE;  in dpm_rrp()
88 	/* POL is 0 */  in dpm_rrp()
89 	ret[1] = 0;  in dpm_rrp()
91 	i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);  in dpm_rrp()
93 		debug("RRP_OPCODE returned success data is %x\n", ret[0]);  in dpm_rrp()
94 		return ret[0];  in dpm_rrp()
105 	ret[0] = WRM_OPCODE;  in dpm_wrm()
108 	i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);  in dpm_wrm()
109 	if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */  in dpm_wrm()
110 		debug("WRM_OPCODE returned success data is %x\n", ret[0]);  in dpm_wrm()
111 		return ret[0];  in dpm_wrm()
122 	ret[0] = WRP_OPCODE;  in dpm_wrp()
124 	ret[1] = 0x01;  in dpm_wrp()
125 	ret[2] = 0x00;  in dpm_wrp()
126 	ret[3] = 0x00;  in dpm_wrp()
127 	ret[4] = 0x00;  in dpm_wrp()
130 	i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);  in dpm_wrp()
131 	if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */  in dpm_wrp()
132 		debug("WRP_OPCODE returned success data is %x\n", ret[0]);  in dpm_wrp()
133 		return 0;  in dpm_wrp()
173 	u8 reg = 0x7, vid;  in zm_write_voltage()
193 	u8 reg = 0x7;  in zm_read_voltage()
211 	/* Disable using Write-Protect register 0x96 */  in zm_disable_wp()
212 	new_wp_value = 0x8;  in zm_disable_wp()
213 	if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) {  in zm_disable_wp()
217 	return 0;  in zm_disable_wp()
223 	orig_wp_value = 0x0;  in zm_enable_wp()
225 	/* Enable using Write-Protect register 0x96 */  in zm_enable_wp()
226 	if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) {  in zm_enable_wp()
230 	return 0;  in zm_enable_wp()