Lines Matching refs:vid
284 u8 vid; in set_voltage_to_IR() local
291 vid = DIV_ROUND_UP(vdd - 265, 5); in set_voltage_to_IR()
293 vid = DIV_ROUND_UP(vdd - 245, 5); in set_voltage_to_IR()
297 1, (void *)&vid, sizeof(vid)); in set_voltage_to_IR()
377 u8 vid, buf; in adjust_vdd() local
379 u8 vid; in adjust_vdd() local
495 u8 vid; in adjust_vdd() member
535 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & in adjust_vdd()
537 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { in adjust_vdd()
538 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & in adjust_vdd()
541 vdd_target = vdd[vid]; in adjust_vdd()
633 u8 vid, buf; in adjust_vdd() local
667 u8 vid; in adjust_vdd() member
725 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & in adjust_vdd()
727 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { in adjust_vdd()
728 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & in adjust_vdd()
732 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & in adjust_vdd()
734 if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { in adjust_vdd()
735 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & in adjust_vdd()
739 vdd_target = vdd[vid]; in adjust_vdd()