Lines Matching +full:sata +full:- +full:cold
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
39 struct cpu_type *cpu = gd->arch.cpu; in checkboard()
44 printf("Board: %sQDS, ", cpu->name); in checkboard()
118 return -1; in read_voltage()
180 ret = -1; in adjust_vdd()
185 fusesr = in_be32(&gur->dcfg_fusesr); in adjust_vdd()
221 ret = -1; in adjust_vdd()
229 ret = -1; in adjust_vdd()
244 no need to re-set */ in adjust_vdd()
258 ret = -1; in adjust_vdd()
266 temp_voltage = existing_voltage - ZM_STEP; in adjust_vdd()
270 temp_voltage -= ZM_STEP; in adjust_vdd()
277 ret = -1; in adjust_vdd()
293 ret = -1; in adjust_vdd()
300 ret = -1; in adjust_vdd()
312 ret = -1; in adjust_vdd()
321 ret = -1; in adjust_vdd()
338 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & in configure_vsc3316_3308()
347 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & in configure_vsc3316_3308()
491 return -1; in configure_vsc3316_3308()
590 return -1; in configure_vsc3316_3308()
601 * or PLL power-up procedure in calibrate_pll()
604 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
607 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
610 setbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
612 setbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
619 rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) & in calibrate_pll()
637 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
639 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & in check_pll_locks()
642 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & in check_pll_locks()
645 setbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
647 dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) & in check_pll_locks()
654 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in check_pll_locks()
657 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
659 setbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
663 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
665 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) in check_pll_locks()
668 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) in check_pll_locks()
671 setbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
674 (&srds_regs->bank[pll_num].pllsr2) & in check_pll_locks()
679 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in check_pll_locks()
682 setbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
684 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
686 setbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
690 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
693 (&srds_regs->bank[pll_num].pllcr1)| in check_pll_locks()
695 out_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
697 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
700 (&srds_regs->bank[pll_num].pllcr0)| in check_pll_locks()
702 out_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
711 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in check_pll_locks()
717 setbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
719 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
721 pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)| in check_pll_locks()
723 out_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
725 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
727 pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)| in check_pll_locks()
729 out_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
731 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
733 setbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
782 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & in config_serdes1_refclks()
786 return -1; in config_serdes1_refclks()
795 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); in config_serdes1_refclks()
876 clrbits_be32(&srds_regs->bank[i].rstctl, in config_serdes1_refclks()
879 clrbits_be32(&srds_regs->bank[i].rstctl, in config_serdes1_refclks()
882 setbits_be32(&srds_regs->bank[i].rstctl, in config_serdes1_refclks()
884 setbits_be32(&srds_regs->bank[i].rstctl, in config_serdes1_refclks()
899 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); in config_serdes1_refclks()
912 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & in config_serdes2_refclks()
916 return -ENODEV; in config_serdes2_refclks()
925 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); in config_serdes2_refclks()
927 /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work in config_serdes2_refclks()
939 debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n", in config_serdes2_refclks()
960 clrbits_be32(&srds2_regs->bank[i].rstctl, in config_serdes2_refclks()
963 clrbits_be32(&srds2_regs->bank[i].rstctl, in config_serdes2_refclks()
966 setbits_be32(&srds2_regs->bank[i].rstctl, in config_serdes2_refclks()
968 setbits_be32(&srds2_regs->bank[i].rstctl, in config_serdes2_refclks()
984 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); in config_serdes2_refclks()
1003 * Remap Boot flash + PROMJET region to caching-inhibited in board_early_init_r()
1007 /* Flush d-cache and invalidate i-cache of any FLASH data */ in board_early_init_r()
1011 if (flash_esel == -1) { in board_early_init_r()
1043 * are not suitable for PCIe SATA to work in board_early_init_r()
1046 * for PCIe SATA to work in board_early_init_r()
1051 else if (ret == -ENODEV) in board_early_init_r()
1060 * and at cold temperatures. in board_early_init_r()
1115 int ret = -1; in serdes_refclock()
1146 ret = -1; in serdes_refclock()
1179 u32 pllcr0 = srds_regs->bank[i].pllcr0; in misc_init_r()