35 	u32 msize = 0;  in dram_init()
41 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;  in dram_init()
53 	msize = get_ram_size(0, msize);  in dram_init()
58 	return 0;  in dram_init()
69 	return 0;  in checkboard()
88 	return 0;  in ft_board_setup()
96 	clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);  in misc_init_r()
98 	return 0;  in misc_init_r()
106 #define SMALL_RAM	0xff
107 #define LARGE_RAM	0x00
109 #define SMALL_RAM	0x00
110 #define LARGE_RAM	0xff
116 	SPD_VAL(0x80, 0x80),	/* 00 use 128 Bytes */
117 	SPD_VAL(0x07, 0x07),	/* 01 use 128 Bytes */
119 	SPD_VAL(0x0d, 0x0d),	/* 03 rows: 13 */
120 	SPD_VAL(0x09, 0x0a),	/* 04 cols:  9 / 10 */
121 	SPD_VAL(0x00, 0x00),	/* 05 */
122 	SPD_VAL(0x40, 0x40),	/* 06 */
123 	SPD_VAL(0x00, 0x00),	/* 07 */
124 	SPD_VAL(0x05, 0x05),	/* 08 */
125 	SPD_VAL(0x30, 0x30),	/* 09 */
126 	SPD_VAL(0x45, 0x45),	/* 10 */
127 	SPD_VAL(0x02, 0x02),	/* 11 ecc used */
128 	SPD_VAL(0x82, 0x82),	/* 12 */
129 	SPD_VAL(0x10, 0x10),	/* 13 */
130 	SPD_VAL(0x08, 0x08),	/* 14 */
131 	SPD_VAL(0x00, 0x00),	/* 15 */
132 	SPD_VAL(0x0c, 0x0c),	/* 16 */
133 	SPD_VAL(0x04, 0x08),	/* 17 banks: 4 / 8 */
134 	SPD_VAL(0x38, 0x38),	/* 18 */
135 	SPD_VAL(0x00, 0x00),	/* 19 */
136 	SPD_VAL(0x02, 0x02),	/* 20 */
137 	SPD_VAL(0x00, 0x00),	/* 21 */
138 	SPD_VAL(0x03, 0x03),	/* 22 */
139 	SPD_VAL(0x3d, 0x3d),	/* 23 */
140 	SPD_VAL(0x45, 0x45),	/* 24 */
141 	SPD_VAL(0x50, 0x50),	/* 25 */
142 	SPD_VAL(0x45, 0x45),	/* 26 */
143 	SPD_VAL(0x3c, 0x3c),	/* 27 */
144 	SPD_VAL(0x28, 0x28),	/* 28 */
145 	SPD_VAL(0x3c, 0x3c),	/* 29 */
146 	SPD_VAL(0x2d, 0x2d),	/* 30 */
147 	SPD_VAL(0x20, 0x80),	/* 31 */
148 	SPD_VAL(0x20, 0x20),	/* 32 */
149 	SPD_VAL(0x27, 0x27),	/* 33 */
150 	SPD_VAL(0x10, 0x10),	/* 34 */
151 	SPD_VAL(0x17, 0x17),	/* 35 */
152 	SPD_VAL(0x3c, 0x3c),	/* 36 */
153 	SPD_VAL(0x1e, 0x1e),	/* 37 */
154 	SPD_VAL(0x1e, 0x1e),	/* 38 */
155 	SPD_VAL(0x00, 0x00),	/* 39 */
156 	SPD_VAL(0x00, 0x06),	/* 40 */
157 	SPD_VAL(0x37, 0x37),	/* 41 */
158 	SPD_VAL(0x4b, 0x7f),	/* 42 */
159 	SPD_VAL(0x80, 0x80),	/* 43 */
160 	SPD_VAL(0x18, 0x18),	/* 44 */
161 	SPD_VAL(0x22, 0x22),	/* 45 */
162 	SPD_VAL(0x00, 0x00),	/* 46 */
163 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
164 	SPD_VAL(0x10, 0x10),	/* 62 */
165 	SPD_VAL(0x7e, 0x1d),	/* 63 */
167 	SPD_VAL(0x00, 0x00),	/* 72 */
179 	int valid = 0;  in vme8349_read_spd()
181 	i2c_set_bus_num(0);  in vme8349_read_spd()
183 	if (i2c_read(chip, addr, alen, buffer, len) == 0)  in vme8349_read_spd()
184 		if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {  in vme8349_read_spd()
185 			sum = 0;  in vme8349_read_spd()
186 			for (l = 0; l < 63; l++)  in vme8349_read_spd()
187 				sum = (sum + buffer[l]) & 0xff;  in vme8349_read_spd()
195 	if (valid == 0) {  in vme8349_read_spd()
197 		sum = 0;  in vme8349_read_spd()
198 		for (l = 0; l < 63; l++)  in vme8349_read_spd()
199 			sum = (sum + buffer[l]) & 0xff;  in vme8349_read_spd()
208 	return 0;  in vme8349_read_spd()