43                 return 0;  in board_fit_config_name_match()
45                 return 0;  in board_fit_config_name_match()
47                 return 0;  in board_fit_config_name_match()
49                 return 0;  in board_fit_config_name_match()
51                 return 0;  in board_fit_config_name_match()
53                 return 0;  in board_fit_config_name_match()
81 	spl_boot_list[0] = boot_dev;  in board_boot_order()
92 	return 0;  in spl_start_uboot()
99  *   0x30 == 40 Ohm
100  *   0x28 == 48 Ohm
102 #define IMX6DQ_DRIVE_STRENGTH		0x30
103 #define IMX6SDL_DRIVE_STRENGTH		0x28
130 	.dram_sdba2 = 0x00000000,
146 	.grp_ddrmode_ctl = 0x00020000,
147 	.grp_ddrpke = 0x00000000,
148 	.grp_ddrmode = 0x00020000,
150 	.grp_ddr_type = 0x000c0000,
162 	.dram_sdba2 = 0x00000000,
185 	.grp_ddr_type = 0x000c0000,
186 	.grp_ddrmode_ctl = 0x00020000,
187 	.grp_ddrpke = 0x00000000,
190 	.grp_ddrmode = 0x00020000,
213 	.SRT = 0,
217 	.p0_mpwldectrl0 = 0x000E0009,
218 	.p0_mpwldectrl1 = 0x0018000E,
219 	.p1_mpwldectrl0 = 0x00000007,
220 	.p1_mpwldectrl1 = 0x00000000,
221 	.p0_mpdgctrl0 = 0x43280334,
222 	.p0_mpdgctrl1 = 0x031C0314,
223 	.p1_mpdgctrl0 = 0x4318031C,
224 	.p1_mpdgctrl1 = 0x030C0258,
225 	.p0_mprddlctl = 0x3E343A40,
226 	.p1_mprddlctl = 0x383C3844,
227 	.p0_mpwrdlctl = 0x40404440,
228 	.p1_mpwrdlctl = 0x4C3E4446,
235 	.cs1_mirror	= 0,
243 	.walat		= 0,
245 	.rst_to_cke	= 0x23,
246 	.sde_to_rst	= 0x10,
250 	.p0_mpwldectrl0 = 0x001F0024,
251 	.p0_mpwldectrl1 = 0x00110018,
252 	.p1_mpwldectrl0 = 0x001F0024,
253 	.p1_mpwldectrl1 = 0x00110018,
254 	.p0_mpdgctrl0 = 0x4230022C,
255 	.p0_mpdgctrl1 = 0x02180220,
256 	.p1_mpdgctrl0 = 0x42440248,
257 	.p1_mpdgctrl1 = 0x02300238,
258 	.p0_mprddlctl = 0x44444A48,
259 	.p1_mprddlctl = 0x46484A42,
260 	.p0_mpwrdlctl = 0x38383234,
261 	.p1_mpwrdlctl = 0x3C34362E,
267 	.cs1_mirror	= 0,
275 	.walat		= 0,
277 	.rst_to_cke	= 0x23,
278 	.sde_to_rst	= 0x10,
284 	.cs1_mirror	= 0,
292 	.walat		= 0,
294 	.rst_to_cke	= 0x23,
295 	.sde_to_rst	= 0x10,
301 	.grp_addds = 0x00000030,
302 	.grp_ddrmode_ctl = 0x00020000,
303 	.grp_b0ds = 0x00000030,
304 	.grp_ctlds = 0x00000030,
305 	.grp_b1ds = 0x00000030,
306 	.grp_ddrpke = 0x00000000,
307 	.grp_ddrmode = 0x00020000,
308 	.grp_ddr_type = 0x000c0000,
312 	.dram_dqm0 = 0x00000030,
313 	.dram_dqm1 = 0x00000030,
314 	.dram_ras = 0x00000030,
315 	.dram_cas = 0x00000030,
316 	.dram_odt0 = 0x00000030,
317 	.dram_odt1 = 0x00000030,
318 	.dram_sdba2 = 0x00000000,
319 	.dram_sdclk_0 = 0x00000008,
320 	.dram_sdqs0 = 0x00000038,
321 	.dram_sdqs1 = 0x00000030,
322 	.dram_reset = 0x00000030,
326 	.p0_mpwldectrl0 = 0x00070007,
327 	.p0_mpdgctrl0 = 0x41490145,
328 	.p0_mprddlctl = 0x40404546,
329 	.p0_mpwrdlctl = 0x4040524D,
333 	.dsize = 0,
336 	.cs1_mirror = 0,
343 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
344 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
371 	writel(0x00003F3F, &ccm->CCGR0);  in ccgr_init()
372 	writel(0x0030FC00, &ccm->CCGR1);  in ccgr_init()
373 	writel(0x000FC000, &ccm->CCGR2);  in ccgr_init()
374 	writel(0x3F300000, &ccm->CCGR3);  in ccgr_init()
375 	writel(0xFF00F300, &ccm->CCGR4);  in ccgr_init()
376 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
377 	writel(0x000003CC, &ccm->CCGR6);  in ccgr_init()
379 	writel(0x00c03f3f, &ccm->CCGR0);  in ccgr_init()
380 	writel(0xfcffff00, &ccm->CCGR1);  in ccgr_init()
381 	writel(0x0cffffcc, &ccm->CCGR2);  in ccgr_init()
382 	writel(0x3f3c3030, &ccm->CCGR3);  in ccgr_init()
383 	writel(0xff00fffc, &ccm->CCGR4);  in ccgr_init()
384 	writel(0x033f30ff, &ccm->CCGR5);  in ccgr_init()
385 	writel(0x00c00fff, &ccm->CCGR6);  in ccgr_init()