Lines Matching +full:de +full:- +full:skew
1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
35 # bit3-0: 0 required
39 # bit11-7: 0 required
43 # bit17-15: 0 required
46 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
47 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
48 # bit30-28: 3 required
52 # bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
53 # bit7-4: 5, 6 cycle tRCD
54 # bit11-8: 4, 5 cyle tRP
55 # bit15-12: 5, 6 cyle tWR
56 # bit19-16: 2, 3 cyle tWTR
58 # bit23-21: 0 required
59 # bit27-24: 2, 3 cycle tRRD
60 # bit31-28: 2, 3 cyle tRTP
63 # bit6-0: 0x33, 33 cycle tRFC
64 # bit8-7: 0, 1 cycle tR2R
65 # bit10-9: 0, 1 cyle tR2W
66 # bit12-11: 1, 2 cylce tW2W
67 # bit31-13: 0 required
70 # bit1-0: 0, Cs0width=x8
71 # bit3-2: 3, Cs0size=1Gb
72 # bit5-4: 0, Cs1width=nonexistent
73 # bit7-6: 0, Cs1size=nonexistent
74 # bit9-8: 0, Cs2width=nonexistent
75 # bit11-10: 0, Cs2size=nonexistent
76 # bit13-12: 0, Cs3width=nonexistent
77 # bit15-14: 0, Cs3size=nonexistent
82 # bit31-20: 0 required
86 # bit31-1: 0 required
89 # bit3-0: 0, Cmd=Normal SDRAM Mode
90 # bit31-4: 0 required
93 # bit2-0: 2, Burst Length (2 required)
95 # bit6-4: 5, CAS Latency (CL) 5
98 # bit11-9: 0, Write recovery for auto-precharge (3 required ??)
100 # bit31-13: 0 required
106 # bit5-3: 0 required
108 # bit9-7: 0 required
112 # bit31-13: 0 required
115 # bit2-0: 0x7 required
117 # bit6-4: 0x7 required
121 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
122 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
123 # bit15-12: 0xf required
124 # bit31-16: 0 required
127 # bit3-0: 0 required
128 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
129 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
130 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
131 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
132 # bit31-20: 0 required
135 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
136 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
137 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
138 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
139 # bit31-16: 0 required
145 # bit3-2: 0x0, CS0 hit selected
146 # bit23-4: 0xfffff required
147 # bit31-24: 0x0f, Size (i.e. 256MB)
153 # bit3-2: 1, CS1 hit selected
154 # bit23-4: 0xfffff required
155 # bit31-24: 0x0f, Size (i.e. 256MB)
161 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
162 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
163 # bit15-8: 0 required
164 # bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
165 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
166 # bit31-24: 0 required
169 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
170 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
171 # bit31-4 0 required
174 # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
175 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
176 # bit9-8: 0, Internal ODT assertion is controlled by fiels
177 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
178 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
181 # bit20-16: 0, Pad N channel driving strength for ODT
182 # bit25-21: 0, Pad P channel driving strength for ODT
183 # bit31-26: 0 required
187 # bit31-1: 0, required