1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2010-2017 CS Systemes d'Information
4  * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
5  * Christophe Leroy <christophe.leroy@c-s.fr>
23 	/* DRAM - single read. (offset 0 in upm RAM) */
27 	/* DRAM - burst read. (offset 8 in upm RAM) */
33 	/* DRAM - single write. (offset 18 in upm RAM) */
37 	/* DRAM - burst write. (offset 20 in upm RAM) */
56 	const char *sync = "receive";  in ft_board_setup()  local
61 	do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",  in ft_board_setup()
62 			     bd->bi_busfreq, 1);  in ft_board_setup()
68 	do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);  in ft_board_setup()
70 	/* E1 interface - Set data rate */  in ft_board_setup()
71 	do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);  in ft_board_setup()
73 	/* E1 interface - Set channel phase to 0 */  in ft_board_setup()
74 	do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);  in ft_board_setup()
76 	/* E1 interface - rising edge sync pulse transmit */  in ft_board_setup()
77 	do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",  in ft_board_setup()
78 			 sync, strlen(sync), 1);  in ft_board_setup()
93 	memctl8xx_t __iomem *memctl = &immap->im_memctl;  in dram_init()
101 	out_be16(&memctl->memc_mptpr, 0x0200);  in dram_init()
102 	out_be32(&memctl->memc_mamr, 0x14904000);  in dram_init()
104 	out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);  in dram_init()
105 	out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);  in dram_init()
107 	out_be32(&memctl->memc_mcr, 0x80002830);  in dram_init()
108 	out_be32(&memctl->memc_mar, 0x00000088);  in dram_init()
109 	out_be32(&memctl->memc_mcr, 0x80002038);  in dram_init()
112 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,  in dram_init()
121 	iop8xx_t __iomem *iop = &immr->im_ioport;  in misc_init_r()
124 	clrbits_be16(&iop->iop_pcpar, 0x4);  in misc_init_r()
125 	clrbits_be16(&iop->iop_pcdir, 0x4);  in misc_init_r()
128 	if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)  in misc_init_r()
141 	clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */  in board_early_init_f()
142 	setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */  in board_early_init_f()
144 	setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */  in board_early_init_f()