22 	USDHC1_BASE_ADDR, 0, 4};
38 	.init1		= 0x00690000,
39 	.init0		= 0x00020083,
40 	.init3		= 0x09300004,
41 	.init4		= 0x04080000,
42 	.init5		= 0x00100004,
43 	.rankctl	= 0x0000033F,
44 	.dramtmg1	= 0x0007020E,
45 	.dramtmg2	= 0x03040407,
46 	.dramtmg3	= 0x00002006,
47 	.dramtmg4	= 0x04020305,
48 	.dramtmg5	= 0x03030202,
49 	.dramtmg8	= 0x00000803,
50 	.zqctl0		= 0x00810021,
51 	.dfitmg0	= 0x02098204,
52 	.dfitmg1	= 0x00030303,
53 	.dfiupd0	= 0x80400003,
54 	.dfiupd1	= 0x00100020,
55 	.dfiupd2	= 0x80100004,
56 	.addrmap4	= 0x00000F0F,
57 	.odtcfg		= 0x06000604,
58 	.odtmap		= 0x00000001,
62 	.pctrl_0	= 0x00000001,
66 	.phy_con0	= 0x17420F40,
67 	.phy_con1	= 0x10210100,
68 	.phy_con4	= 0x00060807,
69 	.mdll_con0	= 0x1010007E,
70 	.drvds_con0	= 0x00000D6E,
71 	.cmd_sdll_con0	= 0x00000010,
72 	.offset_lp_con0	= 0x0000000F,
78 		0x0E407304,
79 		0x0E447304,
80 		0x0E447306,
81 		0x0E447304,
82 		0x0E407304,
90 		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01041001;  in cl_som_imx7_spl_dram_cfg_size()
91 		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x00400046;  in cl_som_imx7_spl_dram_cfg_size()
92 		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E1109;  in cl_som_imx7_spl_dram_cfg_size()
93 		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000014;  in cl_som_imx7_spl_dram_cfg_size()
94 		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00151515;  in cl_som_imx7_spl_dram_cfg_size()
95 		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x03030303;  in cl_som_imx7_spl_dram_cfg_size()
96 		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x0F0F0303;  in cl_som_imx7_spl_dram_cfg_size()
97 		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0C0C0C0C;  in cl_som_imx7_spl_dram_cfg_size()
98 		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x04040404;  in cl_som_imx7_spl_dram_cfg_size()
101 		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01040001;  in cl_som_imx7_spl_dram_cfg_size()
102 		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x00400046;  in cl_som_imx7_spl_dram_cfg_size()
103 		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E1109;  in cl_som_imx7_spl_dram_cfg_size()
104 		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000015;  in cl_som_imx7_spl_dram_cfg_size()
105 		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00161616;  in cl_som_imx7_spl_dram_cfg_size()
106 		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x04040404;  in cl_som_imx7_spl_dram_cfg_size()
107 		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x0F0F0404;  in cl_som_imx7_spl_dram_cfg_size()
108 		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0C0C0C0C;  in cl_som_imx7_spl_dram_cfg_size()
109 		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x04040404;  in cl_som_imx7_spl_dram_cfg_size()
112 		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01040001;  in cl_som_imx7_spl_dram_cfg_size()
113 		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x00400046;  in cl_som_imx7_spl_dram_cfg_size()
114 		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E1109;  in cl_som_imx7_spl_dram_cfg_size()
115 		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000016;  in cl_som_imx7_spl_dram_cfg_size()
116 		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00171717;  in cl_som_imx7_spl_dram_cfg_size()
117 		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x04040404;  in cl_som_imx7_spl_dram_cfg_size()
118 		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x0F040404;  in cl_som_imx7_spl_dram_cfg_size()
119 		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0A0A0A0A;  in cl_som_imx7_spl_dram_cfg_size()
120 		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x02020202;  in cl_som_imx7_spl_dram_cfg_size()
123 		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01040001;  in cl_som_imx7_spl_dram_cfg_size()
124 		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x0040005E;  in cl_som_imx7_spl_dram_cfg_size()
125 		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E110A;  in cl_som_imx7_spl_dram_cfg_size()
126 		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000018;  in cl_som_imx7_spl_dram_cfg_size()
127 		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00181818;  in cl_som_imx7_spl_dram_cfg_size()
128 		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x04040404;  in cl_som_imx7_spl_dram_cfg_size()
129 		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x04040404;  in cl_som_imx7_spl_dram_cfg_size()
130 		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0A0A0A0A;  in cl_som_imx7_spl_dram_cfg_size()
131 		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x04040404;  in cl_som_imx7_spl_dram_cfg_size()
143 	ulong ram_size_test, ram_size = 0;  in cl_som_imx7_spl_dram_cfg()
182 	memset(__bss_start, 0, __bss_end - __bss_start);  in board_init_f()
184 	board_init_r(NULL, 0);  in board_init_f()
201 	spl_boot_list[0] = spl_boot_device();  in board_boot_order()
202 	switch (spl_boot_list[0]) {  in board_boot_order()