Lines Matching +full:ouput +full:- +full:only

1 // SPDX-License-Identifier: GPL-2.0+
28 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;  in board_init()
46 	 * chip.  So only one MDIO channel can access the PHY chip at a time and  in board_init()
51 	 * GPIOS[1:0] -> MDC1 & MDIO1  in board_init()
52 	 * GPIOB[5:4] -> MDC2 & MDIO2  in board_init()
53 	 * GPIOA[1:0] -> MDC3 & MDIO3  in board_init()
54 	 * GPIOA[3:2] -> MDC4 & MDIO4  in board_init()
67 	 * set 32 GPIO ouput pins for ATE report   in board_init()
68 	 *   GPIOV[7:0] -> ATE[7:0]  in board_init()
69 	 *   GPIOY[3:0] -> ATE[11:8]  in board_init()
70 	 *   GPIOM[3:0] -> ATE[15:12]  in board_init()
71 	 *   GPIOH[3:0] -> ATE[19:16]  in board_init()
72 	 *   GPIOB[3:0] -> ATE[23:20]  in board_init()
73 	 *   GPIOM[5:4] -> ATE[25:24]  in board_init()
74 	 *   GPION[5:0] -> ATE[31:26]  in board_init()