Lines Matching +full:0 +full:x414

8 #define SCU_BASE	0x1e6e2000
9 #define ESPI_BASE 0x1e6ee000
10 #define LPC_BASE 0x1e789000
11 #define LPC_HICR5 (LPC_BASE + 0x80)
12 #define LPC_HICR6 (LPC_BASE + 0x84)
13 #define LPC_SNPWADR (LPC_BASE + 0x90)
14 #define LPC_HICRB (LPC_BASE + 0x100)
15 #define GPIO_BASE 0x1e780000
20 #define HICR5_SEL80HGIO (0x1f << 24) /* Select 80hGIO */
21 #define SET_SEL80HGIO(x) ((x & 0x1f) << 24) /* Select 80hGIO Offset */
22 #define HICR5_UNKVAL_MASK 0x1FFF0000 /* Bits with unknown values on reset */
23 #define HICR5_ENINT_SNP0W (1 << 1) /* Enable Snooping address 0 */
24 #define HICR5_EN_SNP0W (1 << 0) /* Enable Snooping address 0 */
27 #define HICR6_STR_SNP0W (1 << 0) /* Interrupt Status Snoop address 0 */
37 /* set lpc snoop #0 to port 0x80 */ in port80h_snoop_init()
38 value = readl(LPC_SNPWADR) & 0xffff0000; in port80h_snoop_init()
39 writel(value | 0x80, LPC_SNPWADR); in port80h_snoop_init()
46 /* enable lpc snoop #0 and SIOGIO */ in port80h_snoop_init()
61 #define GPIO554 0x554 in sgpio_init()
62 #define SCU_414 0x414 /* Multi-function Pin Control #5 */ in sgpio_init()
78 reg = readl(SCU_BASE + 0x510); in espi_init()
101 reg = readl(ESPI_BASE + 0x000); in espi_init()
102 reg |= 0xef; in espi_init()
103 writel(reg, ESPI_BASE + 0x000); in espi_init()
105 writel(0x0, ESPI_BASE + 0x110); in espi_init()
106 writel(0x0, ESPI_BASE + 0x114); in espi_init()
108 reg = readl(ESPI_BASE + 0x00c); in espi_init()
109 reg |= 0x80000000; in espi_init()
110 writel(reg, ESPI_BASE + 0x00c); in espi_init()
112 writel(0xffffffff, ESPI_BASE + 0x094); in espi_init()
113 writel(0x1, ESPI_BASE + 0x100); in espi_init()
114 writel(0x1, ESPI_BASE + 0x120); in espi_init()
116 reg = readl(ESPI_BASE + 0x080); in espi_init()
117 reg |= 0x50; in espi_init()
118 writel(reg, ESPI_BASE + 0x080); in espi_init()
120 reg = readl(ESPI_BASE + 0x000); in espi_init()
121 reg |= 0x10; in espi_init()
122 writel(reg, ESPI_BASE + 0x000); in espi_init()
127 #if 0 in board_early_init_f()
132 return 0; in board_early_init_f()