Lines Matching +full:0 +full:x00000064
23 #define V3_PCI_VENDOR 0x00000000
24 #define V3_PCI_DEVICE 0x00000002
25 #define V3_PCI_CMD 0x00000004
26 #define V3_PCI_STAT 0x00000006
27 #define V3_PCI_CC_REV 0x00000008
28 #define V3_PCI_HDR_CFG 0x0000000C
29 #define V3_PCI_IO_BASE 0x00000010
30 #define V3_PCI_BASE0 0x00000014
31 #define V3_PCI_BASE1 0x00000018
32 #define V3_PCI_SUB_VENDOR 0x0000002C
33 #define V3_PCI_SUB_ID 0x0000002E
34 #define V3_PCI_ROM 0x00000030
35 #define V3_PCI_BPARAM 0x0000003C
36 #define V3_PCI_MAP0 0x00000040
37 #define V3_PCI_MAP1 0x00000044
38 #define V3_PCI_INT_STAT 0x00000048
39 #define V3_PCI_INT_CFG 0x0000004C
40 #define V3_LB_BASE0 0x00000054
41 #define V3_LB_BASE1 0x00000058
42 #define V3_LB_MAP0 0x0000005E
43 #define V3_LB_MAP1 0x00000062
44 #define V3_LB_BASE2 0x00000064
45 #define V3_LB_MAP2 0x00000066
46 #define V3_LB_SIZE 0x00000068
47 #define V3_LB_IO_BASE 0x0000006E
48 #define V3_FIFO_CFG 0x00000070
49 #define V3_FIFO_PRIORITY 0x00000072
50 #define V3_FIFO_STAT 0x00000074
51 #define V3_LB_ISTAT 0x00000076
52 #define V3_LB_IMASK 0x00000077
53 #define V3_SYSTEM 0x00000078
54 #define V3_LB_CFG 0x0000007A
55 #define V3_PCI_CFG 0x0000007C
56 #define V3_DMA_PCI_ADR0 0x00000080
57 #define V3_DMA_PCI_ADR1 0x00000090
58 #define V3_DMA_LOCAL_ADR0 0x00000084
59 #define V3_DMA_LOCAL_ADR1 0x00000094
60 #define V3_DMA_LENGTH0 0x00000088
61 #define V3_DMA_LENGTH1 0x00000098
62 #define V3_DMA_CSR0 0x0000008B
63 #define V3_DMA_CSR1 0x0000009B
64 #define V3_DMA_CTLB_ADR0 0x0000008C
65 #define V3_DMA_CTLB_ADR1 0x0000009C
66 #define V3_DMA_DELAY 0x000000E0
67 #define V3_MAIL_DATA 0x000000C0
68 #define V3_PCI_MAIL_IEWR 0x000000D0
69 #define V3_PCI_MAIL_IERD 0x000000D2
70 #define V3_LB_MAIL_IEWR 0x000000D4
71 #define V3_LB_MAIL_IERD 0x000000D6
72 #define V3_MAIL_WR_STAT 0x000000D8
73 #define V3_MAIL_RD_STAT 0x000000DA
74 #define V3_QBA_MAP 0x000000DC
83 #define V3_COMMAND_M_IO_EN (1 << 0)
102 #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
103 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
106 #define V3_PCI_BASE_M_IO (1 << 0)
110 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
114 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
116 #define V3_PCI_MAP_M_ENABLE (1 << 0)
118 #define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4)
134 #define V3_LB_BASE_ADR_BASE 0xfff00000
138 #define V3_LB_BASE_ENABLE (1 << 0)
140 #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
158 #define V3_LB_MAP_MAP_ADR 0xfff0
160 #define V3_LB_MAP_AD_LOW_EN (1 << 0)
162 #define V3_LB_MAP_TYPE_IACK (0 << 1)
174 #define V3_LB_BASE2_ADR_BASE 0xff00
176 #define V3_LB_BASE2_ENABLE (1 << 0)
183 #define V3_LB_MAP2_MAP_ADR 0xff00