Lines Matching full:dis
33 { CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */
34 { CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */
35 { CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */
37 { HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */
51 { MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */
52 { MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */
53 { MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */
54 { MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */
55 { MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */
56 { MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */
57 { MCSPI1_CS3, (IDIS | DIS | M7) }, /* safe_mode */
59 { UART3_CTS_RCTX, (IDIS | DIS | M7) }, /* safe_mode */
60 { UART3_RTS_SD, (IDIS | DIS | M7) }, /* safe_mode */
61 { UART3_RX_IRRX, (IEN | DIS | M0) }, /* uart3_rx_irrx */
62 { UART3_TX_IRTX, (IDIS | DIS | M0) }, /* uart3_tx_irtx */
71 { MCSPI4_CLK, (IEN | DIS | M0) }, /* mcspi4_clk */
72 { MCSPI4_SIMO, (IEN | DIS | M0) }, /* mcspi4_simo */
73 { MCSPI4_SOMI, (IEN | DIS | M0) }, /* mcspi4_somi */
76 { UART4_RX, (IDIS | DIS | M4) }, /* gpio_155 */
77 { UART4_TX, (IDIS | DIS | M7) }, /* safe_mode */
79 { UNIPRO_TX0, (IDIS | DIS | M7) }, /* safe_mode */
80 { UNIPRO_TY0, (IDIS | DIS | M7) }, /* safe_mode */
81 { UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */
82 { UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */
83 { UNIPRO_TX2, (IDIS | DIS | M7) }, /* safe_mode */
84 { UNIPRO_TY2, (IDIS | DIS | M7) }, /* safe_mode */
85 { UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */
86 { UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */
87 { UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */
88 { UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */
89 { UNIPRO_RX2, (IDIS | DIS | M7) }, /* safe_mode */
90 { UNIPRO_RY2, (IDIS | DIS | M7) }, /* safe_mode */
93 { USBA0_OTG_DP, (IEN | DIS | M0) }, /* usba0_otg_dp */
94 { USBA0_OTG_DM, (IEN | DIS | M0) }, /* usba0_otg_dm */