asm/arch-de212/tie.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
8  * Copyright (C) 1999-2015 Cadence Design Systems Inc.
19 /*  Save area for non-coprocessor optional and custom (TIE) state:  */
24 #define XCHAL_TOTAL_SA_SIZE		32	/* with 16-byte align padding */
37  *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
41  *	galign = group byte alignment (power of 2) (galign >= align)
42  *	align = register byte alignment (power of 2)
45  *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
47  *	regnum = reg index in regfile, or special/TIE-user reg number
54  *  To filter out certain registers, e.g. to expand only the non-global
69  XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
71  XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \
72  XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
73  XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
74  XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
75  XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0)
101 /* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
103 /* Byte length of instruction from its first byte, per FLIX.  */