asm/arch-dc233c/tie.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
8  * Copyright (C) 1999-2010 Tensilica Inc.
42 /*  Save area for non-coprocessor optional and custom (TIE) state:  */
43 #define XCHAL_NCP_SA_SIZE		32
47 #define XCHAL_TOTAL_SA_SIZE		32	/* with 16-byte align padding */
60  *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
64  *	galign = group byte alignment (power of 2) (galign >= align)
65  *	align = register byte alignment (power of 2)
68  *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
70  *	regnum = reg index in regfile, or special/TIE-user reg number
77  *  To filter out certain registers, e.g. to expand only the non-global
92  XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
93  XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
95  XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
96  XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
97  XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
98  XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0) \
99  XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0)
125 /* Byte length of instruction from its first nibble (op0 field), per FLIX.  */