Lines Matching +full:8 +full:- +full:4 +full:- +full:4 +full:- +full:4 +full:- +full:12
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2008 - 2013 Tensilica Inc.
4 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
12 #include <asm-offsets.h>
20 #define PT_PS 4
21 #define PT_DEPC 8
22 #define PT_EXCCAUSE 12
60 .align 4
72 * that DDR has been set up before running U-Boot. (See also comments
78 .align 4
156 l32i a5, a2, 4 # end destination (in RAM)
157 l32i a6, a2, 8 # start source (in ROM)
158 addi a2, a2, 12 # next entry
174 srli a8, a8, 4
175 slli a8, a8, 4
181 srli a8, a8, 4
182 slli a8, a8, 4
190 addi a6, a6, 4
192 addi a4, a4, 4
223 .align 4
228 movi sp, (XTENSA_SYS_TEXT_ADDR - 16) & 0xfffffff0
287 .align 4
311 /* Reserve 16-byte save area */
312 addi sp, a2, -16
326 * - We currently don't use the user exception vector (PS.UM is always 0),
329 * - We currently only save the bare minimum number of registers:
330 * a0...a15, sar, loop-registers, exception register (epc1, excvaddr,
332 * - WINDOWSTART is only saved to identify if registers have been spilled
372 .align 4
382 addi a1, a1, -16 - 4 # create a small stack frame
391 1: addi a2, a1, - PT_SIZE - 16
392 s32i a0, a2, PT_AREG + 0 * 4
393 s32i a1, a2, PT_AREG + 1 * 4
394 s32i a3, a2, PT_AREG + 3 * 4
396 s32i a3, a2, PT_AREG + 2 * 4
401 s32i a4, a1, PT_AREG + 4 * 4
402 s32i a5, a1, PT_AREG + 5 * 4
403 s32i a6, a1, PT_AREG + 6 * 4
404 s32i a7, a1, PT_AREG + 7 * 4
405 s32i a8, a1, PT_AREG + 8 * 4
406 s32i a9, a1, PT_AREG + 9 * 4
407 s32i a10, a1, PT_AREG + 10 * 4
408 s32i a11, a1, PT_AREG + 11 * 4
409 s32i a12, a1, PT_AREG + 12 * 4
410 s32i a13, a1, PT_AREG + 13 * 4
411 s32i a14, a1, PT_AREG + 14 * 4
412 s32i a15, a1, PT_AREG + 15 * 4
490 addi a3, a2, -1
495 addi a3, a2, -1
499 addi a2, a1, -16
501 l32i a5, a2, 4
503 s32i a5, a1, PT_SIZE + 4
504 l32i a4, a2, 8
505 l32i a5, a2, 12
506 s32i a4, a1, PT_SIZE + 8
507 s32i a5, a1, PT_SIZE + 12
512 1: l32i a15, a1, PT_AREG + 15 * 4
513 l32i a14, a1, PT_AREG + 14 * 4
514 l32i a13, a1, PT_AREG + 13 * 4
515 l32i a12, a1, PT_AREG + 12 * 4
516 l32i a11, a1, PT_AREG + 11 * 4
517 l32i a10, a1, PT_AREG + 10 * 4
518 l32i a9, a1, PT_AREG + 9 * 4
519 l32i a8, a1, PT_AREG + 8 * 4
520 l32i a7, a1, PT_AREG + 7 * 4
521 l32i a6, a1, PT_AREG + 6 * 4
522 l32i a5, a1, PT_AREG + 5 * 4
523 l32i a4, a1, PT_AREG + 4 * 4
524 l32i a3, a1, PT_AREG + 3 * 4
525 l32i a2, a1, PT_AREG + 2 * 4
526 l32i a0, a1, PT_AREG + 0 * 4
528 l32i a1, a1, PT_AREG + 1 * 4 # Remove ptrace stack frame
539 * handlers underflow-4 to underflow-12, then the overflow handlers
540 * overflow-4 to overflow-12.
548 /* 4-Register Window Overflow Vector (Handler) */
553 s32e a0, a5, -16
554 s32e a1, a5, -12
555 s32e a2, a5, -8
556 s32e a3, a5, -4
560 /* 4-Register Window Underflow Vector (Handler) */
565 l32e a0, a5, -16
566 l32e a1, a5, -12
567 l32e a2, a5, -8
568 l32e a3, a5, -4
573 * a1: new stack pointer = a1 - 16 - 4
592 /* 43*/ addi a1, a1, 16 + 4
595 /* 49*/ rotw -1
597 /* 55*/ rotw -1
602 /* 8-Register Window Overflow Vector (Handler) */
607 s32e a0, a9, -16
608 l32e a0, a1, -12
609 s32e a2, a9, -8
610 s32e a1, a9, -12
611 s32e a3, a9, -4
612 s32e a4, a0, -32
613 s32e a5, a0, -28
614 s32e a6, a0, -24
615 s32e a7, a0, -20
618 /* 8-Register Window Underflow Vector (Handler) */
623 l32e a1, a9, -12
624 l32e a0, a9, -16
625 l32e a7, a1, -12
626 l32e a2, a9, -8
627 l32e a4, a7, -32
628 l32e a3, a9, -4
629 l32e a5, a7, -28
630 l32e a6, a7, -24
631 l32e a7, a7, -20
634 /* 12-Register Window Overflow Vector (Handler) */
639 s32e a0, a13, -16
640 l32e a0, a1, -12
641 s32e a1, a13, -12
642 s32e a2, a13, -8
643 s32e a3, a13, -4
644 s32e a4, a0, -48
645 s32e a5, a0, -44
646 s32e a6, a0, -40
647 s32e a7, a0, -36
648 s32e a8, a0, -32
649 s32e a9, a0, -28
650 s32e a10, a0, -24
651 s32e a11, a0, -20
654 /* 12-Register Window Underflow Vector (Handler) */
656 .org _WindowOverflow12 + 64 - 3
658 rotw -1
661 l32e a1, a13, -12
662 l32e a0, a13, -16
663 l32e a11, a1, -12
664 l32e a2, a13, -8
665 l32e a4, a11, -48
666 l32e a8, a11, -32
667 l32e a3, a13, -4
668 l32e a5, a11, -44
669 l32e a6, a11, -40
670 l32e a7, a11, -36
671 l32e a9, a11, -28
672 l32e a10, a11, -24
673 l32e a11, a11, -20