Lines Matching +full:0 +full:xd8
16 #define SPIBAR_OFFSET 0x3800
20 #define SPIBAR_SSFC 0x91
21 #define SPIBAR_FDOC 0xb0
22 #define SPIBAR_FDOD 0xb4
24 #define SPIBAR_PREOP 0x94
25 #define SPIBAR_OPTYPE 0x96
26 #define SPIBAR_OPMENU_LOWER 0x98
27 #define SPIBAR_OPMENU_UPPER 0x9c
29 #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
30 #define SPI_OPTYPE_0 0x01 /* Write, no address */
32 #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
33 #define SPI_OPTYPE_1 0x03 /* Write, address required */
35 #define SPI_OPMENU_2 0x03 /* READ: Read Data */
36 #define SPI_OPTYPE_2 0x02 /* Read, address required */
38 #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
39 #define SPI_OPTYPE_3 0x00 /* Read, no address */
41 #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
42 #define SPI_OPTYPE_4 0x03 /* Write, address required */
44 #define SPI_OPMENU_5 0x9f /* RDID: Read ID */
45 #define SPI_OPTYPE_5 0x00 /* Read, no address */
47 #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
48 #define SPI_OPTYPE_6 0x03 /* Write, address required */
50 #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
51 #define SPI_OPTYPE_7 0x02 /* Read, address required */
63 #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
65 #define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
70 #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
71 #define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
72 #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
73 #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
76 #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
77 #define SPIBAR_FADDR 0x08 /* SPI flash address */
78 #define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
79 #define SPIBAR_SSFS 0x90
82 #define SPIBAR_SSFC 0x91