Lines Matching +full:gpio +full:- +full:lvl
1 // SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch-baytrail/fsp/fsp_configs.h>
8 #include <dt-bindings/gpio/x86-gpio.h>
9 #include <dt-bindings/interrupt-router/intel-irq.h>
22 compatible = "intel,x86-pinctrl";
25 /* Add UART1 PAD configuration (SIO HS-UART) */
27 pad-offset = <0x10>;
28 mode-func = <1>;
32 pad-offset = <0x20>;
33 mode-func = <1>;
40 * the pin to work in GPIO mode, which causes card detect
47 pad-offset = <0x3a0>;
48 mode-func = <1>;
52 gpio-offset = <0xa0 10>;
53 pad-offset = <0x23b0>;
54 mode-func = <0>;
55 mode-gpio;
56 output-value = <1>;
62 stdout-path = "/serial";
66 #address-cells = <1>;
67 #size-cells = <0>;
71 compatible = "intel,baytrail-cpu";
73 intel,apic-id = <0>;
78 compatible = "intel,baytrail-cpu";
80 intel,apic-id = <2>;
85 compatible = "intel,baytrail-cpu";
87 intel,apic-id = <4>;
92 compatible = "intel,baytrail-cpu";
94 intel,apic-id = <6>;
99 compatible = "intel,pci-baytrail", "pci-x86";
100 #address-cells = <3>;
101 #size-cells = <2>;
102 u-boot,dm-pre-reloc;
113 u-boot,dm-pre-reloc;
115 reg-shift = <2>;
116 clock-frequency = <58982400>;
117 current-speed = <115200>;
123 #address-cells = <1>;
124 #size-cells = <1>;
126 irq-router {
127 compatible = "intel,irq-router";
128 intel,pirq-config = "ibase";
129 intel,ibase-offset = <0x50>;
130 intel,actl-addr = <0>;
131 intel,pirq-link = <8 8>;
132 intel,pirq-mask = <0xdee0>;
133 intel,pirq-routing = <
192 #address-cells = <1>;
193 #size-cells = <0>;
194 compatible = "intel,ich9-spi";
195 spi-flash@0 {
196 #address-cells = <1>;
197 #size-cells = <1>;
200 "spi-flash";
201 memory-map = <0xff800000 0x00800000>;
202 rw-mrc-cache {
203 label = "rw-mrc-cache";
210 compatible = "intel,ich6-gpio";
211 u-boot,dm-pre-reloc;
213 bank-name = "A";
214 use-lvl-write-cache;
218 compatible = "intel,ich6-gpio";
219 u-boot,dm-pre-reloc;
221 bank-name = "B";
222 use-lvl-write-cache;
226 compatible = "intel,ich6-gpio";
227 u-boot,dm-pre-reloc;
229 bank-name = "C";
230 use-lvl-write-cache;
234 compatible = "intel,ich6-gpio";
235 u-boot,dm-pre-reloc;
237 bank-name = "D";
238 use-lvl-write-cache;
242 compatible = "intel,ich6-gpio";
243 u-boot,dm-pre-reloc;
245 bank-name = "E";
246 use-lvl-write-cache;
250 compatible = "intel,ich6-gpio";
251 u-boot,dm-pre-reloc;
253 bank-name = "F";
254 use-lvl-write-cache;
260 compatible = "intel,baytrail-fsp";
261 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
262 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
263 fsp,mrc-init-spd-addr1 = <0xa0>;
264 fsp,mrc-init-spd-addr2 = <0xa2>;
265 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
266 fsp,enable-sdio;
267 fsp,enable-sdcard;
268 fsp,enable-hsuart0;
269 fsp,enable-hsuart1;
270 fsp,enable-spi;
271 fsp,enable-sata;
272 fsp,sata-mode = <SATA_MODE_AHCI>;
274 fsp,enable-xhci;
276 fsp,lpe-mode = <LPE_MODE_PCI>;
277 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
278 fsp,enable-dma0;
279 fsp,enable-dma1;
280 fsp,enable-i2c0;
281 fsp,enable-i2c1;
282 fsp,enable-i2c2;
283 fsp,enable-i2c3;
284 fsp,enable-i2c4;
285 fsp,enable-i2c5;
286 fsp,enable-i2c6;
287 fsp,enable-pwm0;
288 fsp,enable-pwm1;
289 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
290 fsp,aperture-size = <APERTURE_SIZE_256MB>;
291 fsp,gtt-size = <GTT_SIZE_2MB>;
292 fsp,scc-mode = <SCC_MODE_PCI>;
293 fsp,os-selection = <OS_SELECTION_LINUX>;
294 fsp,emmc45-ddr50-enabled;
295 fsp,emmc45-retune-timer-value = <8>;
296 fsp,enable-igd;
297 fsp,enable-memory-down;
298 fsp,memory-down-params {
299 compatible = "intel,baytrail-fsp-mdp";
300 fsp,dram-speed = <DRAM_SPEED_1333MTS>;
301 fsp,dram-type = <DRAM_TYPE_DDR3L>;
302 fsp,dimm-0-enable;
303 fsp,dimm-width = <DIMM_WIDTH_X16>;
304 fsp,dimm-density = <DIMM_DENSITY_8GBIT>;
305 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
306 fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
308 /* These following values might need a re-visit */
309 fsp,dimm-tcl = <8>;
310 fsp,dimm-trpt-rcd = <8>;
311 fsp,dimm-twr = <8>;
312 fsp,dimm-twtr = <4>;
313 fsp,dimm-trrd = <6>;
314 fsp,dimm-trtp = <4>;
315 fsp,dimm-tfaw = <22>;