Lines Matching +full:gpio +full:- +full:lvl
1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
9 #include <asm/arch-baytrail/fsp/fsp_configs.h>
10 #include <dt-bindings/gpio/x86-gpio.h>
11 #include <dt-bindings/interrupt-router/intel-irq.h>
20 model = "congatec-QEVAL20-QA3-E3845";
21 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
33 compatible = "intel,x86-pinctrl";
40 * the pin to work in GPIO mode, which causes card detect
47 pad-offset = <0x3a0>;
48 mode-func = <1>;
53 pad-offset = <0x580>;
54 mode-func = <1>;
58 pad-offset = <0x5a0>;
59 mode-func = <1>;
64 stdout-path = "/serial";
68 #address-cells = <1>;
69 #size-cells = <0>;
73 compatible = "intel,baytrail-cpu";
75 intel,apic-id = <0>;
80 compatible = "intel,baytrail-cpu";
82 intel,apic-id = <2>;
87 compatible = "intel,baytrail-cpu";
89 intel,apic-id = <4>;
94 compatible = "intel,baytrail-cpu";
96 intel,apic-id = <6>;
101 compatible = "intel,pci-baytrail", "pci-x86";
102 #address-cells = <3>;
103 #size-cells = <2>;
104 u-boot,dm-pre-reloc;
112 #address-cells = <1>;
113 #size-cells = <1>;
115 irq-router {
116 compatible = "intel,irq-router";
117 intel,pirq-config = "ibase";
118 intel,ibase-offset = <0x50>;
119 intel,actl-addr = <0>;
120 intel,pirq-link = <8 8>;
121 intel,pirq-mask = <0xdee0>;
122 intel,pirq-routing = <
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "intel,ich9-spi";
184 spi-flash@0 {
185 #address-cells = <1>;
186 #size-cells = <1>;
189 "spi-flash";
190 memory-map = <0xff800000 0x00800000>;
191 rw-mrc-cache {
192 label = "rw-mrc-cache";
199 compatible = "intel,ich6-gpio";
200 u-boot,dm-pre-reloc;
202 bank-name = "A";
203 use-lvl-write-cache;
207 compatible = "intel,ich6-gpio";
208 u-boot,dm-pre-reloc;
210 bank-name = "B";
211 use-lvl-write-cache;
215 compatible = "intel,ich6-gpio";
216 u-boot,dm-pre-reloc;
218 bank-name = "C";
219 use-lvl-write-cache;
223 compatible = "intel,ich6-gpio";
224 u-boot,dm-pre-reloc;
226 bank-name = "D";
227 use-lvl-write-cache;
231 compatible = "intel,ich6-gpio";
232 u-boot,dm-pre-reloc;
234 bank-name = "E";
235 use-lvl-write-cache;
239 compatible = "intel,ich6-gpio";
240 u-boot,dm-pre-reloc;
242 bank-name = "F";
243 use-lvl-write-cache;
249 compatible = "intel,baytrail-fsp";
250 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
251 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
252 fsp,mrc-init-spd-addr1 = <0xa0>;
253 fsp,mrc-init-spd-addr2 = <0xa2>;
254 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
255 fsp,enable-sdio;
256 fsp,enable-sdcard;
257 fsp,enable-hsuart1;
258 fsp,enable-spi;
259 fsp,enable-sata;
260 fsp,sata-mode = <SATA_MODE_AHCI>;
262 fsp,enable-xhci;
264 fsp,lpe-mode = <LPE_MODE_PCI>;
265 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
266 fsp,enable-dma0;
267 fsp,enable-dma1;
268 fsp,enable-pwm0;
269 fsp,enable-pwm1;
270 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
271 fsp,aperture-size = <APERTURE_SIZE_256MB>;
272 fsp,gtt-size = <GTT_SIZE_2MB>;
273 fsp,scc-mode = <SCC_MODE_PCI>;
274 fsp,os-selection = <OS_SELECTION_LINUX>;
275 fsp,emmc45-ddr50-enabled;
276 fsp,emmc45-retune-timer-value = <8>;
277 fsp,enable-igd;
278 fsp,enable-memory-down;
279 fsp,memory-down-params {
280 compatible = "intel,baytrail-fsp-mdp";
281 fsp,dram-speed = <DRAM_SPEED_1333MTS>;
282 fsp,dram-type = <DRAM_TYPE_DDR3L>;
283 fsp,dimm-0-enable;
284 fsp,dimm-1-enable;
285 fsp,dimm-width = <DIMM_WIDTH_X16>;
286 fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
287 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
288 fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
290 /* These following values might need a re-visit */
291 fsp,dimm-tcl = <8>;
292 fsp,dimm-trpt-rcd = <8>;
293 fsp,dimm-twr = <8>;
294 fsp,dimm-twtr = <4>;
295 fsp,dimm-trrd = <6>;
296 fsp,dimm-trtp = <4>;
297 fsp,dimm-tfaw = <22>;