x86/dts/chromebook_link.dts

1 /dts-v1/;
3 #include <dt-bindings/gpio/x86-gpio.h>
4 #include <dt-bindings/sound/azalia.h>
16 	compatible = "google,link", "intel,celeron-ivybridge";
29 		#address-cells = <1>;
30 		#size-cells = <0>;
34 			compatible = "intel,core-gen3";
36 			intel,apic-id = <0>;
41 			compatible = "intel,core-gen3";
43 			intel,apic-id = <1>;
48 			compatible = "intel,core-gen3";
50 			intel,apic-id = <2>;
55 			compatible = "intel,core-gen3";
57 			intel,apic-id = <3>;
63 		stdout-path = "/serial";
67 		intel,duplicate-por;
71 		compatible = "intel,x86-pinctrl";
72 		u-boot,dm-pre-reloc;
76 			gpio-offset = <0 0>;
77 			mode-gpio;
82 			gpio-offset = <0>;
83 			mode-gpio;
85 			output-value = <1>;
89 			gpio-offset = <0 3>;
90 			mode-gpio;
95 			gpio-offset = <0 5>;
96 			mode-gpio;
101 			gpio-offset = <0 6>;
102 			mode-gpio;
104 			output-value = <1>;
108 			gpio-offset = <0 7>;
109 			mode-gpio;
115 			gpio-offset = <0 8>;
116 			mode-gpio;
122 			gpio-offset = <0 9>;
123 			mode-gpio;
128 			u-boot,dm-pre-reloc;
129 			gpio-offset = <0 10>;
130 			mode-gpio;
135 			gpio-offset = <0 11>;
136 			mode-gpio;
141 			gpio-offset = <0 12>;
142 			mode-gpio;
148 			gpio-offset = <0 14>;
149 			mode-gpio;
155 			gpio-offset = <0 15>;
156 			mode-gpio;
162 			gpio-offset = <0 21>;
163 			mode-gpio;
168 			gpio-offset = <0 24>;
169 			mode-gpio;
170 			output-value = <0>;
175 			gpio-offset = <0 28>;
176 			mode-gpio;
181 			gpio-offset = <0x30 4>;
182 			mode-gpio;
184 			output-value = <1>;
188 			u-boot,dm-pre-reloc;
189 			gpio-offset = <0x30 9>;
190 			mode-gpio;
195 			u-boot,dm-pre-reloc;
196 			gpio-offset = <0x30 10>;
197 			mode-gpio;
202 			u-boot,dm-pre-reloc;
203 			gpio-offset = <0x30 11>;
204 			mode-gpio;
209 			gpio-offset = <0x30 25>;
210 			mode-gpio;
215 			gpio-offset = <0x30 28>;
216 			mode-gpio;
218 			output-value = <1>;
224 		compatible = "pci-x86";
225 		#address-cells = <3>;
226 		#size-cells = <2>;
227 		u-boot,dm-pre-reloc;
234 			u-boot,dm-pre-reloc;
235 			compatible = "intel,bd82x6x-northbridge";
236 			board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
239 				u-boot,dm-pre-reloc;
240 				#address-cells = <1>;
241 				#size-cells = <0>;
243 					u-boot,dm-pre-reloc;
279 					u-boot,dm-pre-reloc;
356 			intel,panel-port-select = <1>;
357 			intel,panel-power-cycle-delay = <6>;
358 			intel,panel-power-up-delay = <2000>;
359 			intel,panel-power-down-delay = <500>;
360 			intel,panel-power-backlight-on-delay = <2000>;
361 			intel,panel-power-backlight-off-delay = <2000>;
362 			intel,cpu-backlight = <0x00000200>;
363 			intel,pch-backlight = <0x04000000>;
369 			u-boot,dm-pre-reloc;
374 			compatible = "ehci-pci";
379 			compatible = "intel,bd82x6x-hda";
382 			beep-verbs = <
383 				0x00170500	/* power up codec */
392 				creative_codec: creative-ca0132 {
393 					vendor-id = <PCI_VENDOR_ID_CREATIVE>;
394 					device-id = <PCI_DEVICE_ID_CREATIVE_CA01322>;
397 					vendor-id = <PCI_VENDOR_ID_INTEL>;
398 					device-id = <PCI_DEVICE_ID_INTEL_COUGARPOINT_HDMI>;
405 			compatible = "ehci-pci";
411 			u-boot,dm-pre-reloc;
412 			#address-cells = <1>;
413 			#size-cells = <1>;
414 			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
416 			intel,gpi-routing = <0 0 0 0 0 0 0 2
418 			/* Enable EC SMI source */
419 			intel,alt-gp-smi-enable = <0x0100>;
422 				#address-cells = <1>;
423 				#size-cells = <0>;
424 				compatible = "intel,ich9-spi";
425 				u-boot,dm-pre-reloc;
426 				spi-flash@0 {
427 					#size-cells = <1>;
428 					#address-cells = <1>;
429 					u-boot,dm-pre-reloc;
432 							"spi-flash";
433 					memory-map = <0xff800000 0x00800000>;
434 					rw-mrc-cache {
435 						label = "rw-mrc-cache";
437 						u-boot,dm-pre-reloc;
443 				compatible = "intel,ich6-gpio";
444 				u-boot,dm-pre-reloc;
445 				#gpio-cells = <2>;
446 				gpio-controller;
448 				bank-name = "A";
452 				compatible = "intel,ich6-gpio";
453 				u-boot,dm-pre-reloc;
454 				#gpio-cells = <2>;
455 				gpio-controller;
457 				bank-name = "B";
461 				compatible = "intel,ich6-gpio";
462 				u-boot,dm-pre-reloc;
463 				#gpio-cells = <2>;
464 				gpio-controller;
466 				bank-name = "C";
470 				compatible = "intel,bd82x6x-lpc";
471 				#address-cells = <1>;
472 				#size-cells = <0>;
473 				u-boot,dm-pre-reloc;
474 				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
475 				cros-ec@200 {
476 					compatible = "google,cros-ec";
481 					 * the EC
483 					#address-cells = <1>;
484 					#size-cells = <1>;
487 						erase-value = <0xff>;
494 			compatible = "intel,pantherpoint-ahci";
496 			u-boot,dm-pre-reloc;
497 			intel,sata-mode = "ahci";
498 			intel,sata-port-map = <1>;
499 			intel,sata-port0-gen3-tx = <0x00880a7f>;
503 			compatible = "intel,ich-i2c";
505 			u-boot,dm-pre-reloc;
515 		u-boot,dm-pre-reloc;
517 			u-boot,dm-pre-reloc;
543 		/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x144dc0c2 */
547 		 * Pin Complex (NID 0x0B)  Port-G Analog Unknown
564 		/* Pin Complex (NID 0x10) Port-D 1/8 Black HP Out at Ext Left */
567 		/* Pin Complex (NID 0x11) Port-B Click Mic */
570 		/* Pin Complex (NID 0x12) Port-C Combo Jack Mic or D-Mic */
579 		/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */