Lines Matching +full:gpio +full:- +full:lvl
1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include <asm/arch-baytrail/fsp/fsp_configs.h>
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
33 stdout-path = "/serial";
37 #address-cells = <1>;
38 #size-cells = <0>;
42 compatible = "intel,baytrail-cpu";
44 intel,apic-id = <0>;
49 compatible = "intel,baytrail-cpu";
51 intel,apic-id = <2>;
56 compatible = "intel,baytrail-cpu";
58 intel,apic-id = <4>;
63 compatible = "intel,baytrail-cpu";
65 intel,apic-id = <6>;
70 compatible = "intel,x86-pinctrl";
77 * the pin to work in GPIO mode, which causes card detect
84 pad-offset = <0x3a0>;
85 mode-func = <1>;
90 compatible = "pci-x86";
91 #address-cells = <3>;
92 #size-cells = <2>;
93 u-boot,dm-pre-reloc;
101 #address-cells = <1>;
102 #size-cells = <1>;
104 irq-router {
105 compatible = "intel,irq-router";
106 intel,pirq-config = "ibase";
107 intel,ibase-offset = <0x50>;
108 intel,actl-addr = <0>;
109 intel,pirq-link = <8 8>;
110 intel,pirq-mask = <0xdee0>;
111 intel,pirq-routing = <
170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "intel,ich9-spi";
173 spi-flash@0 {
174 #address-cells = <1>;
175 #size-cells = <1>;
178 "spi-flash";
179 memory-map = <0xff800000 0x00800000>;
180 rw-mrc-cache {
181 label = "rw-mrc-cache";
188 compatible = "intel,ich6-gpio";
189 u-boot,dm-pre-reloc;
191 bank-name = "A";
192 use-lvl-write-cache;
196 compatible = "intel,ich6-gpio";
197 u-boot,dm-pre-reloc;
199 bank-name = "B";
200 use-lvl-write-cache;
204 compatible = "intel,ich6-gpio";
205 u-boot,dm-pre-reloc;
207 bank-name = "C";
208 use-lvl-write-cache;
212 compatible = "intel,ich6-gpio";
213 u-boot,dm-pre-reloc;
215 bank-name = "D";
216 use-lvl-write-cache;
220 compatible = "intel,ich6-gpio";
221 u-boot,dm-pre-reloc;
223 bank-name = "E";
224 use-lvl-write-cache;
228 compatible = "intel,ich6-gpio";
229 u-boot,dm-pre-reloc;
231 bank-name = "F";
232 use-lvl-write-cache;
238 compatible = "intel,baytrail-fsp";
239 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
240 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
241 fsp,mrc-init-spd-addr1 = <0xa0>;
242 fsp,mrc-init-spd-addr2 = <0xa2>;
243 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
244 fsp,enable-sdio;
245 fsp,enable-sdcard;
246 fsp,enable-hsuart1;
247 fsp,enable-spi;
248 fsp,enable-sata;
249 fsp,sata-mode = <SATA_MODE_AHCI>;
250 fsp,lpe-mode = <LPE_MODE_PCI>;
251 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
252 fsp,enable-dma0;
253 fsp,enable-dma1;
254 fsp,enable-i2c0;
255 fsp,enable-i2c1;
256 fsp,enable-i2c2;
257 fsp,enable-i2c3;
258 fsp,enable-i2c4;
259 fsp,enable-i2c5;
260 fsp,enable-i2c6;
261 fsp,enable-pwm0;
262 fsp,enable-pwm1;
263 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
264 fsp,aperture-size = <APERTURE_SIZE_256MB>;
265 fsp,gtt-size = <GTT_SIZE_2MB>;
266 fsp,scc-mode = <SCC_MODE_PCI>;
267 fsp,os-selection = <OS_SELECTION_LINUX>;
268 fsp,emmc45-ddr50-enabled;
269 fsp,emmc45-retune-timer-value = <8>;
270 fsp,enable-igd;