Lines Matching refs:byte_lane
126 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane) in training_message() argument
129 DPF(D_INFO, "CH%01X RK%01X BL%01X\n", channel, rank, byte_lane); in training_message()
138 uint8_t byte_lane, uint32_t pi_count) in set_rcvn() argument
147 channel, rank, byte_lane, pi_count); in set_rcvn()
154 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_rcvn()
156 msk = (byte_lane & 1) ? 0xf00000 : 0xf00; in set_rcvn()
157 temp = (byte_lane & 1) ? (pi_count / HALF_CLK) << 20 : in set_rcvn()
169 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in set_rcvn()
170 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_rcvn()
181 reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_rcvn()
187 msk |= (byte_lane & 1) ? (1 << 5) : (1 << 2); in set_rcvn()
192 msk |= (byte_lane & 1) ? (1 << 11) : (1 << 8); in set_rcvn()
200 training_message(channel, rank, byte_lane); in set_rcvn()
213 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_rcvn() argument
226 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_rcvn()
229 temp >>= (byte_lane & 1) ? 20 : 8; in get_rcvn()
240 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in get_rcvn()
241 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_rcvn()
262 uint8_t byte_lane, uint32_t pi_count) in set_rdqs() argument
270 channel, rank, byte_lane, pi_count); in set_rdqs()
277 reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE; in set_rdqs()
278 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_rdqs()
286 training_message(channel, rank, byte_lane); in set_rdqs()
299 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_rdqs() argument
312 reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE; in get_rdqs()
313 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_rdqs()
332 uint8_t byte_lane, uint32_t pi_count) in set_wdqs() argument
341 channel, rank, byte_lane, pi_count); in set_wdqs()
348 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdqs()
350 msk = (byte_lane & 1) ? 0xf0000 : 0xf0; in set_wdqs()
352 temp <<= (byte_lane & 1) ? 16 : 4; in set_wdqs()
363 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in set_wdqs()
364 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdqs()
375 reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdqs()
381 msk |= (byte_lane & 1) ? (1 << 4) : (1 << 1); in set_wdqs()
386 msk |= (byte_lane & 1) ? (1 << 10) : (1 << 7); in set_wdqs()
394 training_message(channel, rank, byte_lane); in set_wdqs()
407 uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_wdqs() argument
420 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_wdqs()
423 temp >>= (byte_lane & 1) ? 16 : 4; in get_wdqs()
434 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in get_wdqs()
435 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_wdqs()
456 uint8_t byte_lane, uint32_t pi_count) in set_wdq() argument
465 channel, rank, byte_lane, pi_count); in set_wdq()
472 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdq()
474 msk = (byte_lane & 1) ? 0xf000 : 0xf; in set_wdq()
476 temp <<= (byte_lane & 1) ? 12 : 0; in set_wdq()
487 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in set_wdq()
488 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdq()
499 reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in set_wdq()
505 msk |= (byte_lane & 1) ? (1 << 3) : (1 << 0); in set_wdq()
510 msk |= (byte_lane & 1) ? (1 << 9) : (1 << 6); in set_wdq()
518 training_message(channel, rank, byte_lane); in set_wdq()
531 uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_wdq() argument
544 reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_wdq()
547 temp >>= (byte_lane & 1) ? 12 : 0; in get_wdq()
558 reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; in get_wdq()
559 reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + in get_wdq()
936 void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting) in set_vref() argument
938 uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL; in set_vref()
943 channel, byte_lane, setting); in set_vref()
946 (byte_lane >> 1) * DDRIODQ_BL_OFFSET, in set_vref()
964 uint32_t get_vref(uint8_t channel, uint8_t byte_lane) in get_vref() argument
968 uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL; in get_vref()
974 (byte_lane >> 1) * DDRIODQ_BL_OFFSET); in get_vref()