Lines Matching +full:check +full:- +full:dco
1 // SPDX-License-Identifier: Intel
50 /* error check */ in mrc_post_code()
58 /* 1000 MHz clock has 1ns period --> no conversion required */ in delay_n()
70 /* 64-bit math is not an option, just use loops */ in delay_u()
71 while (ms--) in delay_u()
78 u32 dco; in select_mem_mgr() local
82 dco = msg_port_read(MEM_CTLR, DCO); in select_mem_mgr()
83 dco &= ~DCO_PMICTL; in select_mem_mgr()
84 msg_port_write(MEM_CTLR, DCO, dco); in select_mem_mgr()
92 u32 dco; in select_hte() local
96 dco = msg_port_read(MEM_CTLR, DCO); in select_hte()
97 dco |= DCO_PMICTL; in select_hte()
98 msg_port_write(MEM_CTLR, DCO, dco); in select_hte()
116 /* Send DRAM wake command using special MCU side-band WAKE opcode */
151 * BL0 -> B01PTRCTL0[11:08] (0x0-0xF) in set_rcvn()
152 * BL1 -> B01PTRCTL0[23:20] (0x0-0xF) in set_rcvn()
162 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_rcvn()
166 * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F) in set_rcvn()
167 * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F) in set_rcvn()
178 * BL0/1 -> B01DBCTL1[08/11] (+1 select) in set_rcvn()
179 * BL0/1 -> B01DBCTL1[02/05] (enable) in set_rcvn()
198 /* error check */ in set_rcvn()
223 * BL0 -> B01PTRCTL0[11:08] (0x0-0xF) in get_rcvn()
224 * BL1 -> B01PTRCTL0[23:20] (0x0-0xF) in get_rcvn()
237 * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F) in get_rcvn()
238 * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F) in get_rcvn()
274 * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47) in set_rdqs()
275 * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47) in set_rdqs()
284 /* error check (shouldn't go above 0x3F) */ in set_rdqs()
309 * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47) in get_rdqs()
310 * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47) in get_rdqs()
345 * BL0 -> B01PTRCTL0[07:04] (0x0-0xF) in set_wdqs()
346 * BL1 -> B01PTRCTL0[19:16] (0x0-0xF) in set_wdqs()
356 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_wdqs()
360 * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F) in set_wdqs()
361 * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F) in set_wdqs()
372 * BL0/1 -> B01DBCTL1[07/10] (+1 select) in set_wdqs()
373 * BL0/1 -> B01DBCTL1[01/04] (enable) in set_wdqs()
392 /* error check */ in set_wdqs()
417 * BL0 -> B01PTRCTL0[07:04] (0x0-0xF) in get_wdqs()
418 * BL1 -> B01PTRCTL0[19:16] (0x0-0xF) in get_wdqs()
431 * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F) in get_wdqs()
432 * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F) in get_wdqs()
469 * BL0 -> B01PTRCTL0[03:00] (0x0-0xF) in set_wdq()
470 * BL1 -> B01PTRCTL0[15:12] (0x0-0xF) in set_wdq()
480 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_wdq()
484 * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F) in set_wdq()
485 * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F) in set_wdq()
496 * BL0/1 -> B01DBCTL1[06/09] (+1 select) in set_wdq()
497 * BL0/1 -> B01DBCTL1[00/03] (enable) in set_wdq()
516 /* error check */ in set_wdq()
541 * BL0 -> B01PTRCTL0[03:00] (0x0-0xF) in get_wdq()
542 * BL1 -> B01PTRCTL0[15:12] (0x0-0xF) in get_wdq()
555 * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F) in get_wdq()
556 * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F) in get_wdq()
587 * CMDPTRREG[11:08] (0x0-0xF) in set_wcmd()
596 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_wcmd()
600 * CMDDLLPICODER0[29:24] -> CMDSLICE R3 (unused) in set_wcmd()
601 * CMDDLLPICODER0[21:16] -> CMDSLICE L3 (unused) in set_wcmd()
602 * CMDDLLPICODER0[13:08] -> CMDSLICE R2 (unused) in set_wcmd()
603 * CMDDLLPICODER0[05:00] -> CMDSLICE L2 (unused) in set_wcmd()
604 * CMDDLLPICODER1[29:24] -> CMDSLICE R1 (unused) in set_wcmd()
605 * CMDDLLPICODER1[21:16] -> CMDSLICE L1 (0x00-0x3F) in set_wcmd()
606 * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused) in set_wcmd()
607 * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused) in set_wcmd()
639 /* error check */ in set_wcmd()
660 * CMDPTRREG[11:08] (0x0-0xF) in get_wcmd()
672 * CMDDLLPICODER0[29:24] -> CMDSLICE R3 (unused) in get_wcmd()
673 * CMDDLLPICODER0[21:16] -> CMDSLICE L3 (unused) in get_wcmd()
674 * CMDDLLPICODER0[13:08] -> CMDSLICE R2 (unused) in get_wcmd()
675 * CMDDLLPICODER0[05:00] -> CMDSLICE L2 (unused) in get_wcmd()
676 * CMDDLLPICODER1[29:24] -> CMDSLICE R1 (unused) in get_wcmd()
677 * CMDDLLPICODER1[21:16] -> CMDSLICE L1 (0x00-0x3F) in get_wcmd()
678 * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused) in get_wcmd()
679 * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused) in get_wcmd()
708 * CCPTRREG[15:12] -> CLK1 (0x0-0xF) in set_wclk()
709 * CCPTRREG[11:08] -> CLK0 (0x0-0xF) in set_wclk()
717 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_wclk()
721 * ECCB1DLLPICODER0[13:08] -> CLK0 (0x00-0x3F) in set_wclk()
722 * ECCB1DLLPICODER0[21:16] -> CLK1 (0x00-0x3F) in set_wclk()
763 /* error check */ in set_wclk()
784 * CCPTRREG[15:12] -> CLK1 (0x0-0xF) in get_wclk()
785 * CCPTRREG[11:08] -> CLK0 (0x0-0xF) in get_wclk()
797 * ECCB1DLLPICODER0[13:08] -> CLK0 (0x00-0x3F) in get_wclk()
798 * ECCB1DLLPICODER0[21:16] -> CLK1 (0x00-0x3F) in get_wclk()
829 * CCPTRREG[31:28] (0x0-0xF) in set_wctl()
830 * CCPTRREG[27:24] (0x0-0xF) in set_wctl()
838 pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; in set_wctl()
842 * ECCB1DLLPICODER?[29:24] (0x00-0x3F) in set_wctl()
843 * ECCB1DLLPICODER?[29:24] (0x00-0x3F) in set_wctl()
880 /* error check */ in set_wctl()
903 * CCPTRREG[31:28] (0x0-0xF) in get_wctl()
904 * CCPTRREG[27:24] (0x0-0xF) in get_wctl()
916 * ECCB1DLLPICODER?[29:24] (0x00-0x3F) in get_wctl()
917 * ECCB1DLLPICODER?[29:24] (0x00-0x3F) in get_wctl()
951 * (check that this is necessary) in set_vref()
991 * This function will return a 32-bit address in the desired
1019 * It will return an encoded 32-bit date in which each bit corresponds to
1029 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in sample_dqs()
1046 hte_mem_op(address, mrc_params->first_run, in sample_dqs()
1048 mrc_params->first_run = 0; in sample_dqs()
1097 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in find_rising_edge()
1106 mrc_params->first_run = 1; in find_rising_edge()
1142 (SAMPLE_CNT - 1 - sample); in find_rising_edge()
1152 case 0: /* sampled 0->0->0 */ in find_rising_edge()
1153 /* move forward from T3 looking for 0->1 */ in find_rising_edge()
1157 case 1: /* sampled 0->0->1 */ in find_rising_edge()
1158 case 5: /* sampled 1->0->1 (bad duty cycle) *HSD#237503* */ in find_rising_edge()
1159 /* move forward from T2 looking for 0->1 */ in find_rising_edge()
1163 case 2: /* sampled 0->1->0 (bad duty cycle) *HSD#237503* */ in find_rising_edge()
1164 case 3: /* sampled 0->1->1 */ in find_rising_edge()
1165 /* move forward from T1 looking for 0->1 */ in find_rising_edge()
1169 case 4: /* sampled 1->0->0 (assumes BL8, HSD#234975) */ in find_rising_edge()
1170 /* move forward from T3 looking for 0->1 */ in find_rising_edge()
1174 case 6: /* sampled 1->1->0 */ in find_rising_edge()
1175 case 7: /* sampled 1->1->1 */ in find_rising_edge()
1176 /* move backward from T1 looking for 1->0 */ in find_rising_edge()
1200 /* check all each byte lane for proper edge */ in find_rising_edge()
1210 delay[bl] -= 1; in find_rising_edge()
1251 * check for byte lane failures.
1259 * set ret_val based on NUM_BYTE_LANES such that you will check in byte_lane_mask()
1269 * need to adjust the mask for 16-bit mode in byte_lane_mask()
1271 if (mrc_params->channel_width == X16) in byte_lane_mask()
1278 * Check memory executing simple write/read/verify at the specified address.
1287 if (mrc_params->hte_setup) { in check_rw_coarse()
1288 mrc_params->hte_setup = 0; in check_rw_coarse()
1302 * Check memory executing write/read/verify of many data patterns
1311 if (mrc_params->hte_setup) { in check_bls_ex()
1312 mrc_params->hte_setup = 0; in check_bls_ex()
1325 * 32-bit LFSR with characteristic polynomial: X^32 + X^22 +X^2 + X^1
1448 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in print_timings()
1450 DPF(D_INFO, "\n---------------------------"); in print_timings()
1456 if (mrc_params->channel_enables & (1 << channel)) { in print_timings()
1458 if (mrc_params->rank_enables & in print_timings()
1469 DPF(D_INFO, "\n---------------------------"); in print_timings()