Lines Matching +full:non +full:- +full:inverted
1 // SPDX-License-Identifier: Intel
18 * (per-bit or full byte lane).
73 * Execute a basic single-cache-line memory write/read/verify test using simple
81 * assumed configuration is done and we just re-run the test
125 * Examine a single-cache-line memory with write/read/verify test using multiple
126 * data patterns (victim-aggressor algorithm).
135 * @victim_bit: should be 0 as auto-rotate feature is in use
137 * assumed configuration is done and we just re-run the test
225 msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1); in hte_mem_init()
240 /* Write/read then write/read with inverted pattern */ in hte_mem_init()
286 * Execute a basic single-cache-line memory write/read/verify test using simple
292 * assumed configuration is done and we just re-run the test
316 * Examine a single-cache-line memory with write/read/verify test using multiple
317 * data patterns (victim-aggressor algorithm).
322 * assumed configuration is done and we just re-run the test
342 * as aggressors. AVN HTE adds an auto-rotate feature which allows us in hte_write_stress_bit_lanes()
358 * Execute a basic single-cache-line memory write or read.
359 * This is just for receive enable / fine write-levelling purpose.
363 * assumed configuration is done and we just re-run the test
364 * @is_write: when non-zero memory write operation executed, otherwise read