Lines Matching +full:0 +full:- +full:dev
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2008-2009 coresystems GmbH
18 static void common_sata_init(struct udevice *dev, unsigned int port_map) in common_sata_init() argument
25 dm_pci_write_config32(dev, IDE_CONFIG, reg32); in common_sata_init()
28 dm_pci_read_config16(dev, 0x92, ®16); in common_sata_init()
29 reg16 &= ~0x3f; in common_sata_init()
31 dm_pci_write_config16(dev, 0x92, reg16); in common_sata_init()
34 port_map &= 0xff; in common_sata_init()
35 dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); in common_sata_init()
38 static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch) in bd82x6x_sata_init() argument
41 const void *blob = gd->fdt_blob; in bd82x6x_sata_init()
42 int node = dev_of_offset(dev); in bd82x6x_sata_init()
50 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); in bd82x6x_sata_init()
52 "sata_interface_speed_support", 0); in bd82x6x_sata_init()
54 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); in bd82x6x_sata_init()
61 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | in bd82x6x_sata_init()
64 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | in bd82x6x_sata_init()
68 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); in bd82x6x_sata_init()
69 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); in bd82x6x_sata_init()
71 common_sata_init(dev, 0x8000 | port_map); in bd82x6x_sata_init()
73 /* Initialize AHCI memory-mapped space */ in bd82x6x_sata_init()
74 abar = dm_pci_read_bar32(dev, 5); in bd82x6x_sata_init()
77 reg32 = readl(abar + 0x00); in bd82x6x_sata_init()
78 reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ in bd82x6x_sata_init()
79 reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ in bd82x6x_sata_init()
82 reg32 &= ~0x00f00000; in bd82x6x_sata_init()
83 reg32 |= (speed_support & 0x03) << 20; in bd82x6x_sata_init()
85 writel(reg32, abar + 0x00); in bd82x6x_sata_init()
87 writel(port_map, abar + 0x0c); in bd82x6x_sata_init()
88 (void) readl(abar + 0x0c); /* Read back 1 */ in bd82x6x_sata_init()
89 (void) readl(abar + 0x0c); /* Read back 2 */ in bd82x6x_sata_init()
91 reg32 = readl(abar + 0x24); in bd82x6x_sata_init()
92 reg32 &= ~0x00000002; in bd82x6x_sata_init()
93 writel(reg32, abar + 0x24); in bd82x6x_sata_init()
95 reg32 = readl(abar + 0xa0); in bd82x6x_sata_init()
96 reg32 &= ~0x00000005; in bd82x6x_sata_init()
97 writel(reg32, abar + 0xa0); in bd82x6x_sata_init()
102 dm_pci_write_bar32(dev, 5, 0x00000000); in bd82x6x_sata_init()
104 dm_pci_read_config16(dev, PCI_COMMAND, ®16); in bd82x6x_sata_init()
106 dm_pci_write_config16(dev, PCI_COMMAND, reg16); in bd82x6x_sata_init()
108 dm_pci_write_config8(dev, 0x09, 0x80); in bd82x6x_sata_init()
111 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | in bd82x6x_sata_init()
113 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | in bd82x6x_sata_init()
118 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); in bd82x6x_sata_init()
119 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); in bd82x6x_sata_init()
121 common_sata_init(dev, port_map); in bd82x6x_sata_init()
123 debug("SATA: Controller in plain-ide mode\n"); in bd82x6x_sata_init()
126 dm_pci_write_bar32(dev, 5, 0x00000000); in bd82x6x_sata_init()
129 dm_pci_read_config16(dev, PCI_COMMAND, ®16); in bd82x6x_sata_init()
131 dm_pci_write_config16(dev, PCI_COMMAND, reg16); in bd82x6x_sata_init()
134 * Native mode capable on both primary and secondary (0xa) in bd82x6x_sata_init()
135 * OR'ed with enabled (0x50) = 0xf in bd82x6x_sata_init()
137 dm_pci_write_config8(dev, 0x09, 0x8f); in bd82x6x_sata_init()
140 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | in bd82x6x_sata_init()
143 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | in bd82x6x_sata_init()
148 dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); in bd82x6x_sata_init()
149 dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); in bd82x6x_sata_init()
151 common_sata_init(dev, port_map); in bd82x6x_sata_init()
155 port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); in bd82x6x_sata_init()
157 pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx); in bd82x6x_sata_init()
159 port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0); in bd82x6x_sata_init()
161 pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx); in bd82x6x_sata_init()
164 pch_common_sir_write(dev, 0x04, 0x00001600); in bd82x6x_sata_init()
165 pch_common_sir_write(dev, 0x28, 0xa0000033); in bd82x6x_sata_init()
166 reg32 = pch_common_sir_read(dev, 0x54); in bd82x6x_sata_init()
167 reg32 &= 0xff000000; in bd82x6x_sata_init()
168 reg32 |= 0x5555aa; in bd82x6x_sata_init()
169 pch_common_sir_write(dev, 0x54, reg32); in bd82x6x_sata_init()
170 pch_common_sir_write(dev, 0x64, 0xcccc8484); in bd82x6x_sata_init()
171 reg32 = pch_common_sir_read(dev, 0x68); in bd82x6x_sata_init()
172 reg32 &= 0xffff0000; in bd82x6x_sata_init()
173 reg32 |= 0xcccc; in bd82x6x_sata_init()
174 pch_common_sir_write(dev, 0x68, reg32); in bd82x6x_sata_init()
175 reg32 = pch_common_sir_read(dev, 0x78); in bd82x6x_sata_init()
176 reg32 &= 0x0000ffff; in bd82x6x_sata_init()
177 reg32 |= 0x88880000; in bd82x6x_sata_init()
178 pch_common_sir_write(dev, 0x78, reg32); in bd82x6x_sata_init()
179 pch_common_sir_write(dev, 0x84, 0x001c7000); in bd82x6x_sata_init()
180 pch_common_sir_write(dev, 0x88, 0x88338822); in bd82x6x_sata_init()
181 pch_common_sir_write(dev, 0xa0, 0x001c7000); in bd82x6x_sata_init()
182 pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c); in bd82x6x_sata_init()
183 pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c); in bd82x6x_sata_init()
184 pch_common_sir_write(dev, 0xd4, 0x10000000); in bd82x6x_sata_init()
186 pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000); in bd82x6x_sata_init()
187 pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100); in bd82x6x_sata_init()
190 static void bd82x6x_sata_enable(struct udevice *dev) in bd82x6x_sata_enable() argument
192 const void *blob = gd->fdt_blob; in bd82x6x_sata_enable()
193 int node = dev_of_offset(dev); in bd82x6x_sata_enable()
196 u16 map = 0; in bd82x6x_sata_enable()
202 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); in bd82x6x_sata_enable()
204 map = 0x0060; in bd82x6x_sata_enable()
205 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); in bd82x6x_sata_enable()
207 map |= (port_map ^ 0x3f) << 8; in bd82x6x_sata_enable()
208 dm_pci_write_config16(dev, 0x90, map); in bd82x6x_sata_enable()
211 static int bd82x6x_sata_bind(struct udevice *dev) in bd82x6x_sata_bind() argument
216 if (gd->flags & GD_FLG_RELOC) { in bd82x6x_sata_bind()
217 ret = ahci_bind_scsi(dev, &scsi_dev); in bd82x6x_sata_bind()
222 return 0; in bd82x6x_sata_bind()
225 static int bd82x6x_sata_probe(struct udevice *dev) in bd82x6x_sata_probe() argument
234 if (!(gd->flags & GD_FLG_RELOC)) in bd82x6x_sata_probe()
235 bd82x6x_sata_enable(dev); in bd82x6x_sata_probe()
237 bd82x6x_sata_init(dev, pch); in bd82x6x_sata_probe()
238 ret = ahci_probe_scsi_pci(dev); in bd82x6x_sata_probe()
243 return 0; in bd82x6x_sata_probe()
247 { .compatible = "intel,pantherpoint-ahci" },