30 	stepping = result.eax & 0xf;  in bridge_silicon_revision()
32 	bridge_id &= 0xf0;  in bridge_silicon_revision()
40 	*base = 0;  in get_pcie_bar()
41 	*len = 0;  in get_pcie_bar()
45 	if (!(pciexbar_reg & (1 << 0)))  in get_pcie_bar()
46 		return 0;  in get_pcie_bar()
49 	case 0: /* 256MB */  in get_pcie_bar()
66 	return 0;  in get_pcie_bar()
74 		debug("Adding PCIe config bar base=0x%08x size=0x%x\n",  in add_fixed_resources()
82 	writel(0xffffffff, DMIBAR_REG(0x1c4));  in northbridge_dmi_init()
83 	writel(0xffffffff, DMIBAR_REG(0x1d0));  in northbridge_dmi_init()
87 		clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),  in northbridge_dmi_init()
91 	setbits_le32(DMIBAR_REG(0x238), 1 << 29);  in northbridge_dmi_init()
94 		setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);  in northbridge_dmi_init()
96 		clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);  in northbridge_dmi_init()
97 		setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));  in northbridge_dmi_init()
102 		setbits_le32(DMIBAR_REG(0xd04), 1 << 4);  in northbridge_dmi_init()
104 	setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));  in northbridge_dmi_init()
114 	bridge_type = readl(MCHBAR_REG(0x5f10));  in northbridge_init()
115 	bridge_type &= ~0xff;  in northbridge_init()
119 		clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);  in northbridge_init()
122 		bridge_type |= 0x30;  in northbridge_init()
125 		bridge_type |= 0x20;  in northbridge_init()
127 	writel(bridge_type, MCHBAR_REG(0x5f10));  in northbridge_init()
130 	 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU  in northbridge_init()
147 		writel(msr.lo, MCHBAR_REG(0x59A0));  in northbridge_init()
148 		writel(msr.hi, MCHBAR_REG(0x59A4));  in northbridge_init()
152 	writel(0x00100001, MCHBAR_REG(0x5500));  in northbridge_init()
160 	dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);  in sandybridge_setup_northbridge_bars()
162 	dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);  in sandybridge_setup_northbridge_bars()
163 	/* 64MB - busses 0-63 */  in sandybridge_setup_northbridge_bars()
166 			      (0LL + DEFAULT_PCIEXBAR) >> 32);  in sandybridge_setup_northbridge_bars()
168 	dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);  in sandybridge_setup_northbridge_bars()
171 	dm_pci_write_config8(dev, PAM0, 0x30);  in sandybridge_setup_northbridge_bars()
172 	dm_pci_write_config8(dev, PAM1, 0x33);  in sandybridge_setup_northbridge_bars()
173 	dm_pci_write_config8(dev, PAM2, 0x33);  in sandybridge_setup_northbridge_bars()
174 	dm_pci_write_config8(dev, PAM3, 0x33);  in sandybridge_setup_northbridge_bars()
175 	dm_pci_write_config8(dev, PAM4, 0x33);  in sandybridge_setup_northbridge_bars()
176 	dm_pci_write_config8(dev, PAM5, 0x33);  in sandybridge_setup_northbridge_bars()
177 	dm_pci_write_config8(dev, PAM6, 0x33);  in sandybridge_setup_northbridge_bars()
189 	dm_pci_read_config32(dev, 0xe4, &capid0_a);  in sandybridge_init_iommu()
196 	writel(IOMMU_BASE1 >> 32, MCHBAR_REG(0x5404));  in sandybridge_init_iommu()
197 	writel(IOMMU_BASE1 | 1, MCHBAR_REG(0x5400));  in sandybridge_init_iommu()
198 	writel(IOMMU_BASE2 >> 32, MCHBAR_REG(0x5414));  in sandybridge_init_iommu()
199 	writel(IOMMU_BASE2 | 1, MCHBAR_REG(0x5410));  in sandybridge_init_iommu()
202 	writel(0x80000000, IOMMU_BASE1 + 0xff0);  in sandybridge_init_iommu()
205 	writel(0x20000000, IOMMU_BASE2 + 0xff0);  in sandybridge_init_iommu()
206 	writel(0xa0000000, IOMMU_BASE2 + 0xff0);  in sandybridge_init_iommu()
216 	dm_pci_read_config32(dev, 0xe4, &capid0_a);  in bd82x6x_northbridge_early_init()
218 		dm_pci_read_config8(dev, 0xf3, &reg8);  in bd82x6x_northbridge_early_init()
219 		reg8 &= ~7; /* Clear 2:0 */  in bd82x6x_northbridge_early_init()
222 			reg8 |= 1; /* Set bit 0 */  in bd82x6x_northbridge_early_init()
224 		dm_pci_write_config8(dev, 0xf3, reg8);  in bd82x6x_northbridge_early_init()
235 	return 0;  in bd82x6x_northbridge_early_init()
248 	return 0;  in bd82x6x_northbridge_probe()