229 	setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));  in pch_power_options()
230 	clrbits_le32(RCB_REG(0x3f02), 0xf);  in pch_power_options()
258 	setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));  in cpt_pm_init()
260 	setbits_le32(RCB_REG(0x228c), 1 << 0);  in cpt_pm_init()
261 	setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));  in cpt_pm_init()
262 	setbits_le32(RCB_REG(0x0900), 1 << 14);  in cpt_pm_init()
263 	writel(0xc0388400, RCB_REG(0x2304));  in cpt_pm_init()
264 	setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));  in cpt_pm_init()
265 	setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));  in cpt_pm_init()
266 	clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);  in cpt_pm_init()
267 	writel(0x050f0000, RCB_REG(0x3318));  in cpt_pm_init()
268 	writel(0x04000000, RCB_REG(0x3324));  in cpt_pm_init()
269 	setbits_le32(RCB_REG(0x3340), 0xfffff);  in cpt_pm_init()
270 	setbits_le32(RCB_REG(0x3344), 1 << 1);  in cpt_pm_init()
272 	writel(0x0001c000, RCB_REG(0x3360));  in cpt_pm_init()
273 	writel(0x00061100, RCB_REG(0x3368));  in cpt_pm_init()
274 	writel(0x7f8fdfff, RCB_REG(0x3378));  in cpt_pm_init()
275 	writel(0x000003fc, RCB_REG(0x337c));  in cpt_pm_init()
276 	writel(0x00001000, RCB_REG(0x3388));  in cpt_pm_init()
277 	writel(0x0001c000, RCB_REG(0x3390));  in cpt_pm_init()
278 	writel(0x00000800, RCB_REG(0x33a0));  in cpt_pm_init()
279 	writel(0x00001000, RCB_REG(0x33b0));  in cpt_pm_init()
280 	writel(0x00093900, RCB_REG(0x33c0));  in cpt_pm_init()
281 	writel(0x24653002, RCB_REG(0x33cc));  in cpt_pm_init()
282 	writel(0x062108fe, RCB_REG(0x33d0));  in cpt_pm_init()
283 	clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);  in cpt_pm_init()
284 	writel(0x01010000, RCB_REG(0x3a28));  in cpt_pm_init()
285 	writel(0x01010404, RCB_REG(0x3a2c));  in cpt_pm_init()
286 	writel(0x01041041, RCB_REG(0x3a80));  in cpt_pm_init()
287 	clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);  in cpt_pm_init()
288 	setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */  in cpt_pm_init()
289 	setbits_le32(RCB_REG(0x3a88), 1 << 0);  /* SATA 4/5 disabled */  in cpt_pm_init()
290 	writel(0x00000001, RCB_REG(0x3a6c));  in cpt_pm_init()
291 	clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);  in cpt_pm_init()
292 	clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);  in cpt_pm_init()
293 	writel(0, RCB_REG(0x33c8));  in cpt_pm_init()
294 	setbits_le32(RCB_REG(0x21b0), 0xf);  in cpt_pm_init()
302 	setbits_le32(RCB_REG(0x2238), 1 << 0);  in ppt_pm_init()
303 	setbits_le32(RCB_REG(0x228c), 1 << 0);  in ppt_pm_init()
304 	setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));  in ppt_pm_init()
305 	setbits_le16(RCB_REG(0x0900), 1 << 14);  in ppt_pm_init()
306 	writel(0xc03b8400, RCB_REG(0x2304));  in ppt_pm_init()
307 	setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));  in ppt_pm_init()
308 	setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));  in ppt_pm_init()
309 	clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);  in ppt_pm_init()
310 	writel(0x054f0000, RCB_REG(0x3318));  in ppt_pm_init()
311 	writel(0x04000000, RCB_REG(0x3324));  in ppt_pm_init()
312 	setbits_le32(RCB_REG(0x3340), 0xfffff);  in ppt_pm_init()
313 	setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));  in ppt_pm_init()
314 	writel(0x0001c000, RCB_REG(0x3360));  in ppt_pm_init()
315 	writel(0x00061100, RCB_REG(0x3368));  in ppt_pm_init()
316 	writel(0x7f8fdfff, RCB_REG(0x3378));  in ppt_pm_init()
317 	writel(0x000003fd, RCB_REG(0x337c));  in ppt_pm_init()
318 	writel(0x00001000, RCB_REG(0x3388));  in ppt_pm_init()
319 	writel(0x0001c000, RCB_REG(0x3390));  in ppt_pm_init()
320 	writel(0x00000800, RCB_REG(0x33a0));  in ppt_pm_init()
321 	writel(0x00001000, RCB_REG(0x33b0));  in ppt_pm_init()
322 	writel(0x00093900, RCB_REG(0x33c0));  in ppt_pm_init()
323 	writel(0x24653002, RCB_REG(0x33cc));  in ppt_pm_init()
324 	writel(0x067388fe, RCB_REG(0x33d0));  in ppt_pm_init()
325 	clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);  in ppt_pm_init()
326 	writel(0x01010000, RCB_REG(0x3a28));  in ppt_pm_init()
327 	writel(0x01010404, RCB_REG(0x3a2c));  in ppt_pm_init()
328 	writel(0x01040000, RCB_REG(0x3a80));  in ppt_pm_init()
329 	clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);  in ppt_pm_init()
331 	setbits_le32(RCB_REG(0x3a84), 1 << 24);  in ppt_pm_init()
333 	setbits_le32(RCB_REG(0x3a88), 1 << 0);  in ppt_pm_init()
334 	writel(0x00000001, RCB_REG(0x3a6c));  in ppt_pm_init()
335 	clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);  in ppt_pm_init()
336 	clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);  in ppt_pm_init()
337 	setbits_le32(RCB_REG(0x33a4), (1 << 0));  in ppt_pm_init()
338 	writel(0, RCB_REG(0x33c8));  in ppt_pm_init()
339 	setbits_le32(RCB_REG(0x21b0), 0xf);  in ppt_pm_init()
345 	clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);  in enable_hpet()
353 	setbits_le32(RCB_REG(0x2234), 0xf);  in enable_clock_gating()
364 	reg32 = readl(RCB_REG(CG));  in enable_clock_gating()
377 	writel(reg32, RCB_REG(CG));  in enable_clock_gating()
379 	setbits_le32(RCB_REG(0x38c0), 0x7);  in enable_clock_gating()
380 	setbits_le32(RCB_REG(0x36d4), 0x6680c004);  in enable_clock_gating()
381 	setbits_le32(RCB_REG(0x3564), 0x3);  in enable_clock_gating()
404 	clrbits_le32(RCB_REG(0x2304), 1 << 10);  in pch_fixups()
405 	setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));  in pch_fixups()
406 	setbits_le32(RCB_REG(0x21a8), 0x3);  in pch_fixups()
414 	writel(0x1000, RCB_REG(SPI_DESC_COMP0));  in set_spi_speed()
417 	fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));  in set_spi_speed()
422 	clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);  in set_spi_speed()
493 	setbits_le32(RCB_REG(GCS), 1 >> 5);	/* No reset */  in bd82x6x_lpc_early_init()