1 // SPDX-License-Identifier: GPL-2.0
5  * From coreboot src/soc/intel/broadwell/romstage/raminit.c
11 #include <syscon.h>
39 	pei_data->pei_version = PEI_VERSION;  in broadwell_fill_pei_data()
40 	pei_data->board_type = BOARD_TYPE_ULT;  in broadwell_fill_pei_data()
41 	pei_data->pciexbar = MCFG_BASE_ADDRESS;  in broadwell_fill_pei_data()
42 	pei_data->smbusbar = SMBUS_BASE_ADDRESS;  in broadwell_fill_pei_data()
43 	pei_data->ehcibar = EARLY_EHCI_BAR;  in broadwell_fill_pei_data()
44 	pei_data->xhcibar = EARLY_XHCI_BAR;  in broadwell_fill_pei_data()
45 	pei_data->gttbar = EARLY_GTT_BAR;  in broadwell_fill_pei_data()
46 	pei_data->pmbase = ACPI_BASE_ADDRESS;  in broadwell_fill_pei_data()
47 	pei_data->gpiobase = GPIO_BASE_ADDRESS;  in broadwell_fill_pei_data()
48 	pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;  in broadwell_fill_pei_data()
49 	pei_data->temp_mmio_base = EARLY_TEMP_MMIO;  in broadwell_fill_pei_data()
50 	pei_data->tx_byte = sdram_console_tx_byte;  in broadwell_fill_pei_data()
51 	pei_data->ddr_refresh_2x = 1;  in broadwell_fill_pei_data()
58 	pei_data->usb2_ports[port].length   = length;  in pei_data_usb2_port()
59 	pei_data->usb2_ports[port].enable   = enable;  in pei_data_usb2_port()
60 	pei_data->usb2_ports[port].oc_pin   = oc_pin;  in pei_data_usb2_port()
61 	pei_data->usb2_ports[port].location = location;  in pei_data_usb2_port()
68 	pei_data->usb3_ports[port].enable   = enable;  in pei_data_usb3_port()
69 	pei_data->usb3_ports[port].oc_pin   = oc_pin;  in pei_data_usb3_port()
70 	pei_data->usb3_ports[port].fixed_eq = fixed_eq;  in pei_data_usb3_port()
86 	pei_data->ec_present = 1;  in mainboard_fill_pei_data()
89 	pei_data->dimm_channel0_disabled = 2;  in mainboard_fill_pei_data()
90 	pei_data->dimm_channel1_disabled = 2;  in mainboard_fill_pei_data()
92 	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));  in mainboard_fill_pei_data()
93 	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));  in mainboard_fill_pei_data()
140 	tom = dpr & ~((1 << 20) - 1);  in get_top_of_ram()
145 		tom -= (dpr & DPR_SIZE_MASK) << 16;  in get_top_of_ram()
151  * sdram_find() - Find available memory
160 	struct memory_info *info = &gd->arch.meminfo;  in sdram_find()
183 		return -ENOENT;  in prepare_mrc_cache()
185 	pei_data->saved_data = mrc_cache->data;  in prepare_mrc_cache()
186 	pei_data->saved_data_size = mrc_cache->data_size;  in prepare_mrc_cache()
188 	      pei_data->saved_data, pei_data->saved_data_size,  in prepare_mrc_cache()
189 	      mrc_cache->checksum);  in prepare_mrc_cache()
216 		return -ENODEV;  in dram_init()
228 		return -ENODEV;  in dram_init()
233 	memcpy(pei_data->spd_data[0][0], spd_data, size);  in dram_init()
234 	memcpy(pei_data->spd_data[1][0], spd_data, size);  in dram_init()
240 	debug("PEI version %#x\n", pei_data->pei_version);  in dram_init()
249 	gd->ram_size = gd->arch.meminfo.total_32bit_memory;  in dram_init()
250 	debug("RAM size %llx\n", (unsigned long long)gd->ram_size);  in dram_init()
252 	debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,  in dram_init()
253 	      pei_data->data_to_save);  in dram_init()
255 	if (pei_data->boot_mode != SLEEP_STATE_S3) {  in dram_init()
260 		gd->arch.mrc_output = (char *)pei_data->data_to_save;  in dram_init()
261 		gd->arch.mrc_output_len = pei_data->data_to_save_size;  in dram_init()
263 	gd->arch.pei_meminfo = pei_data->meminfo;  in dram_init()