1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/gpio.h>
16 #include <asm/arch/gpio.h>
17 #include <dt-bindings/gpio/x86-gpio.h>
19 #include <dm/uclass-internal.h>
49 	const void *blob = gd->fdt_blob;  in broadwell_pinctrl_read_configs()
62 			return -ENOSPC;  in broadwell_pinctrl_read_configs()
66 		conf->node = node;  in broadwell_pinctrl_read_configs()
67 		conf->phandle = phandle;  in broadwell_pinctrl_read_configs()
68 		conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio");  in broadwell_pinctrl_read_configs()
69 		if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT)  in broadwell_pinctrl_read_configs()
70 			conf->dir_input = true;  in broadwell_pinctrl_read_configs()
71 		conf->invert = fdtdec_get_bool(blob, node, "invert");  in broadwell_pinctrl_read_configs()
72 		if (fdtdec_get_int(blob, node, "trigger", -1) == TRIGGER_LEVEL)  in broadwell_pinctrl_read_configs()
73 			conf->trigger_level = true;  in broadwell_pinctrl_read_configs()
74 		if (fdtdec_get_int(blob, node, "output-value", -1) == 1)  in broadwell_pinctrl_read_configs()
75 			conf->output_high = true;  in broadwell_pinctrl_read_configs()
76 		conf->sense_disable = fdtdec_get_bool(blob, node,  in broadwell_pinctrl_read_configs()
77 						      "sense-disable");  in broadwell_pinctrl_read_configs()
78 		if (fdtdec_get_int(blob, node, "owner", -1) == OWNER_GPIO)  in broadwell_pinctrl_read_configs()
79 			conf->owner_gpio = true;  in broadwell_pinctrl_read_configs()
80 		if (fdtdec_get_int(blob, node, "route", -1) == ROUTE_SMI)  in broadwell_pinctrl_read_configs()
81 			conf->route_smi = true;  in broadwell_pinctrl_read_configs()
82 		conf->irq_enable = fdtdec_get_bool(blob, node, "irq-enable");  in broadwell_pinctrl_read_configs()
83 		conf->reset_rsmrst = fdtdec_get_bool(blob, node,  in broadwell_pinctrl_read_configs()
84 						     "reset-rsmrst");  in broadwell_pinctrl_read_configs()
85 		if (fdtdec_get_int(blob, node, "pirq-apic", -1) ==  in broadwell_pinctrl_read_configs()
87 			conf->pirq_apic_route = true;  in broadwell_pinctrl_read_configs()
88 		debug("config: phandle=%d\n", phandle);  in broadwell_pinctrl_read_configs()
107 	return -ENOENT;  in broadwell_pinctrl_lookup_phandle()
114 	const void *blob = gd->fdt_blob;  in broadwell_pinctrl_read_pins()
122 		const u32 *prop = fdt_getprop(blob, node, "config", &len);  in broadwell_pinctrl_read_pins()
131 			uint gpio = fdt32_to_cpu(prop[i * 3]);  in broadwell_pinctrl_read_pins()  local
135 			if (gpio >= num_gpios) {  in broadwell_pinctrl_read_pins()
136 				debug("%s: GPIO %d out of range\n", __func__,  in broadwell_pinctrl_read_pins()
137 				      gpio);  in broadwell_pinctrl_read_pins()
138 				return -EDOM;  in broadwell_pinctrl_read_pins()
145 				return -EINVAL;  in broadwell_pinctrl_read_pins()
147 			gpio_conf[gpio] = val |  in broadwell_pinctrl_read_pins()
164 	int set, bit, gpio = 0;  in broadwell_pinctrl_commit()  local
166 	for (gpio = 0; gpio < MAX_GPIOS; gpio++) {  in broadwell_pinctrl_commit()
167 		int confnum = gpio_conf[gpio] & CONF_MASK;  in broadwell_pinctrl_commit()
171 		val = pin->mode_gpio << CONFA_MODE_SHIFT |  in broadwell_pinctrl_commit()
172 			pin->dir_input << CONFA_DIR_SHIFT |  in broadwell_pinctrl_commit()
173 			pin->invert << CONFA_INVERT_SHIFT |  in broadwell_pinctrl_commit()
174 			pin->trigger_level << CONFA_TRIGGER_SHIFT |  in broadwell_pinctrl_commit()
175 			pin->output_high << CONFA_OUTPUT_SHIFT;  in broadwell_pinctrl_commit()
176 		outl(val, &regs->config[gpio].conf_a);  in broadwell_pinctrl_commit()
177 		outl(pin->sense_disable << CONFB_SENSE_SHIFT,  in broadwell_pinctrl_commit()
178 		     &regs->config[gpio].conf_b);  in broadwell_pinctrl_commit()
180 		/* Determine set and bit based on GPIO number */  in broadwell_pinctrl_commit()
181 		set = gpio / GPIO_PER_BANK;  in broadwell_pinctrl_commit()
182 		bit = gpio % GPIO_PER_BANK;  in broadwell_pinctrl_commit()
185 		owner_gpio[set] |= pin->owner_gpio << bit;  in broadwell_pinctrl_commit()
186 		route_smi[set] |= pin->route_smi << bit;  in broadwell_pinctrl_commit()
187 		irq_enable[set] |= pin->irq_enable << bit;  in broadwell_pinctrl_commit()
188 		reset_rsmrst[set] |= pin->reset_rsmrst << bit;  in broadwell_pinctrl_commit()
190 		/* PIRQ to IO-APIC map */  in broadwell_pinctrl_commit()
191 		if (pin->pirq_apic_route)  in broadwell_pinctrl_commit()
192 			pirq2apic |= gpio_conf[gpio] >> PIRQ_SHIFT;  in broadwell_pinctrl_commit()
193 		debug("gpio %d: conf %d, mode_gpio %d, dir_input %d, output_high %d\n",  in broadwell_pinctrl_commit()
194 		      gpio, confnum, pin->mode_gpio, pin->dir_input,  in broadwell_pinctrl_commit()
195 		      pin->output_high);  in broadwell_pinctrl_commit()
199 		outl(owner_gpio[set], &regs->own[set]);  in broadwell_pinctrl_commit()
200 		outl(route_smi[set], &regs->gpi_route[set]);  in broadwell_pinctrl_commit()
201 		outl(irq_enable[set], &regs->gpi_ie[set]);  in broadwell_pinctrl_commit()
202 		outl(reset_rsmrst[set], &regs->rst_sel[set]);  in broadwell_pinctrl_commit()
205 	outl(pirq2apic, &regs->pirq_to_ioxapic);  in broadwell_pinctrl_commit()
222 		return -ENODEV;  in broadwell_pinctrl_probe()
226 	if (gd->flags & GD_FLG_RELOC)  in broadwell_pinctrl_probe()
238 		return -EINVAL;  in broadwell_pinctrl_probe()
250 	 * mentioned will get the first config mentioned in the list.  in broadwell_pinctrl_probe()
268 	{ .compatible = "intel,x86-broadwell-pinctrl",