120 	msr_write(IA32_PERF_CTL, perf_ctl);  in set_max_freq()
248 	msr_write(MSR_VR_CURRENT_CONFIG, msr);  in initialize_vr_config()
282 	msr_write(MSR_VR_MISC_CONFIG, msr);  in initialize_vr_config()
295 	msr_write(MSR_VR_MISC_CONFIG2, msr);  in initialize_vr_config()
426 	msr_write(IA32_PERF_CTL, perf_ctl);  in set_max_ratio()
474 		msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);  in configure_mca()
483 	msr_write(MSR_PIC_MSG_CONTROL, msr);  in enable_lapic_tpr()
501 	msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);  in configure_c_states()
505 	msr_write(MSR_MISC_PWR_MGMT, msr);  in configure_c_states()
511 	msr_write(MSR_POWER_CTL, msr);  in configure_c_states()
516 	msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);  in configure_c_states()
521 	msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);  in configure_c_states()
526 	msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);  in configure_c_states()
531 	msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);  in configure_c_states()
536 	msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);  in configure_c_states()
541 	msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);  in configure_c_states()
552 	msr_write(MSR_IA32_MISC_ENABLE, msr);  in configure_misc()
557 	msr_write(MSR_IA32_THERM_INTERRUPT, msr);  in configure_misc()
562 	msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);  in configure_misc()
579 		msr_write(MSR_TEMPERATURE_TARGET, msr);  in configure_thermal_target()
593 		msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);  in configure_dca_cap()
611 	msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);  in set_energy_perf_bias()
700 	msr_write(MSR_PKG_POWER_LIMIT, limit);  in cpu_set_power_limits()
709 	msr_write(MSR_DDR_RAPL_LIMIT, msr);  in cpu_set_power_limits()
716 		msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);  in cpu_set_power_limits()