1 // SPDX-License-Identifier: GPL-2.0
94 		return -ENODEV;  in arch_cpu_init_dm()
142 	gd->arch.pei_boot_mode = PEI_BOOT_NONE;  in checkcpu()
160  * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
178 	return -ETIMEDOUT;  in pcode_ready()
243 	msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold -  1A */  in initialize_vr_config()
244 	msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold -  5A */  in initialize_vr_config()
245 	msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */  in initialize_vr_config()
246 	msr.hi |= (1 <<  (62 - 32)); /* Enable PSI4 */  in initialize_vr_config()
253 	msr.hi &= ~(0x3ff << (40 - 32));  in initialize_vr_config()
254 	msr.hi |= (0x200 << (40 - 32)); /* 1.0 */  in initialize_vr_config()
258 	msr.hi &= ~(1 << (51 - 32));  in initialize_vr_config()
259 	/* Enable decay mode on C-state entry */  in initialize_vr_config()
260 	msr.hi |= (1 << (52 - 32));  in initialize_vr_config()
262 	msr.hi &= ~(0x3 << (53 - 32));  in initialize_vr_config()
263 	/* Configure the C-state exit ramp rate */  in initialize_vr_config()
264 	ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),  in initialize_vr_config()
265 			      "intel,slow-ramp", -1);  in initialize_vr_config()
266 	if (ramp != -1) {  in initialize_vr_config()
268 		msr.hi |= ((ramp & 0x3) << (53 - 32));  in initialize_vr_config()
270 		msr.hi &= ~(1 << (50 - 32));  in initialize_vr_config()
273 		msr.hi |= (0x01 << (53 - 32));  in initialize_vr_config()
275 		msr.hi |= (1 << (50 - 32));  in initialize_vr_config()
277 	/* Set MIN_VID (31:24) to allow CPU to have full control */  in initialize_vr_config()
279 	min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),  in initialize_vr_config()
280 				 "intel,min-vid", 0);  in initialize_vr_config()
310 	/* A non-zero value initiates the PCODE calibration */  in calibrate_24mhz_bclk()
446 	priv->ht_disabled = num_threads == num_cores;  in broadwell_init()
493 	msr.lo |= (1 << 30);	/* Package c-state Undemotion Enable */  in configure_c_states()
494 	msr.lo |= (1 << 29);	/* Package c-state Demotion Enable */  in configure_c_states()
500 	/* The deepest package c-state defaults to factory-configured value */  in configure_c_states()
504 	msr.lo &= ~(1 << 0);	/* Enable P-state HW_ALL coordination */  in configure_c_states()
508 	msr.lo |= (1 << 18);	/* Enable Energy Perf Bias MSR 0x1b0 */  in configure_c_states()
510 	msr.lo |= (1 << 0);	/* Bi-directional PROCHOT# */  in configure_c_states()
513 	/* C-state Interrupt Response Latency Control 0 - package C3 latency */  in configure_c_states()
518 	/* C-state Interrupt Response Latency Control 1 */  in configure_c_states()
523 	/* C-state Interrupt Response Latency Control 2 - package C6/C7 short */  in configure_c_states()
528 	/* C-state Interrupt Response Latency Control 3 - package C8 */  in configure_c_states()
533 	/* C-state Interrupt Response Latency Control 4 - package C9 */  in configure_c_states()
538 	/* C-state Interrupt Response Latency Control 5 - package C10 */  in configure_c_states()
570 	tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),  in configure_thermal_target()
571 				    "intel,tcc-offset", 0);  in configure_thermal_target()
602 	/* Determine if energy efficient policy is supported */  in set_energy_perf_bias()
607 	/* Energy Policy is bits 3:0 */  in set_energy_perf_bias()
613 	debug("cpu: energy policy set to %u\n", policy);  in set_energy_perf_bias()
637 	/* Set energy policy */  in cpu_core_init()
665 	power_unit = 2 << ((msr.lo & 0xf) - 1);  in cpu_set_power_limits()
725 	info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000;  in broadwell_get_info()
726 	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |  in broadwell_get_info()
739 	if (dev->seq == 0) {  in cpu_x86_broadwell_probe()
755 	{ .compatible = "intel,core-i3-gen5" },