riscv/dts/ae350_64.dts

1 /dts-v1/;
4 	#address-cells = <2>;
5 	#size-cells = <2>;
16 		stdout-path = "uart0:38400n8";
20 		#address-cells = <1>;
21 		#size-cells = <0>;
22 		timebase-frequency = <60000000>;
29 			mmu-type = "riscv,sv39";
30 			clock-frequency = <60000000>;
31 			d-cache-size = <0x8000>;
32 			d-cache-line-size = <32>;
33 			CPU0_intc: interrupt-controller {
34 				#interrupt-cells = <1>;
35 				interrupt-controller;
36 				compatible = "riscv,cpu-intc";
47 		#address-cells = <2>;
48 		#size-cells = <2>;
49 		compatible = "andestech,riscv-ae350-soc";
52 	plic0: interrupt-controller@e4000000 {
54 		#address-cells = <2>;
55 		#interrupt-cells = <2>;
56 		interrupt-controller;
59 		interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
62 	plic1: interrupt-controller@e6400000 {
64 		#address-cells = <2>;
65 		#interrupt-cells = <2>;
66 		interrupt-controller;
69 		interrupts-extended = <&CPU0_intc 3>;
74 			interrupts-extended = <&CPU0_intc 7>;
80 		#clock-cells = <0>;
81 		compatible = "fixed-clock";
82 		clock-frequency = <100000000>;
88 		clock-frequency = <60000000>;
90 		interrupt-parent = <&plic0>;
97 		clock-frequency = <19660800>;
98 		reg-shift = <2>;
99 		reg-offset = <32>;
100 		no-loopback-test = <1>;
101 		interrupt-parent = <&plic0>;
108 		interrupt-parent = <&plic0>;
113 		max-frequency = <100000000>;
114 		clock-freq-min-max = <400000 100000000>;
115 		fifo-depth = <0x10>;
118 		cap-sd-highspeed;
119 		interrupt-parent = <&plic0>;
126 		dma-channels = <8>;
127 		interrupt-parent = <&plic0>;
134 		interrupt-parent = <&plic0>;
146 		interrupt-parent = <&plic0>;
151 		interrupt-parent = <0x2>;
158 		interrupt-parent = <0x2>;
165 		interrupt-parent = <0x2>;
172 		interrupt-parent = <0x2>;
179 		interrupt-parent = <0x2>;
186 		interrupt-parent = <0x2>;
193 		interrupt-parent = <0x2>;
200 		interrupt-parent = <0x2>;
206 		compatible = "cfi-flash";
208 		bank-width = <2>;
209 		device-width = <1>;
215 		#address-cells = <1>;
216 		#size-cells = <0>;
217 		num-cs = <1>;
220 		interrupt-parent = <&plic0>;
222 			compatible = "spi-flash";
223 			spi-max-frequency = <50000000>;
225 			spi-cpol;
226 			spi-cpha;