Lines Matching refs:la
42 la t0, trap_entry
69 la t0, prior_stage_fdt_address
78 la t5, board_init_f
99 la t0, _start
104 la t3, __bss_start
119 la t1, __rel_dyn_start
120 la t2, __rel_dyn_end
144 la t4, __dyn_sym_start
169 la t0, trap_entry
174 la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
176 la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
192 la t0, board_init_r