Lines Matching +full:dma +full:- +full:protection +full:- +full:control
19 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
43 #define MSR_PE (1<<3) /* Protection Enable */
44 #define MSR_PX (1<<2) /* Protection Exclusive Mode */
60 /* Floating Point Status and Control Register (FPSCR) Fields */
67 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
70 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
87 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
88 #define FPSCR_RN 0x00000003 /* FPU rounding control */
96 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
123 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
157 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
159 #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
162 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
165 #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
181 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
182 #define DCWR_COPY 0 /* Copy-back */
183 #define DCWR_WRITE 1 /* Write-through */
211 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
212 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
213 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
214 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
215 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
216 #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
217 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
218 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
219 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
249 #define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
295 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
309 #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
310 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
313 #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
314 #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
316 #define SPRN_MMUCR 0x3b2 /* MMU Control Register */
318 #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
319 #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
320 #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
321 #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
364 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
366 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
372 #define SPRN_TCR 0x3DA /* Timer Control Register */
374 #define SPRN_TCR 0x154 /* Book E Timer Control Register */
377 #define TCR_WP(x) (((64-x)&0x3)<<30)| \
378 (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
386 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
425 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
426 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
433 #define SPRN_ZPR 0x3B0 /* Zone Protection Register */
449 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
485 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
487 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
488 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
491 #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
493 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
494 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
497 #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
500 #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
522 #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
529 #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
550 #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
554 #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
570 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
571 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
572 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
591 /* Short-hand versions for a number of the above SPRNs */
614 #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
615 #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
649 #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
650 #define L2CR SPRN_L2CR /* PPC 750 L2 control register */
659 #define SVR SPRN_SVR /* System-On-Chip Version Register */
684 #define TCR SPRN_TCR /* Timer Control Register */
763 /* Device Control Registers */
767 #define BESR_DSES 0x80000000 /* Data-Side Error Status */
768 #define BESR_DMES 0x40000000 /* DMA Error Status */
776 #define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
777 #define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
778 #define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
779 #define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
780 #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
781 #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
782 #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
783 #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
784 #define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
785 #define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
786 #define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
787 #define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
788 #define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
789 #define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
790 #define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
791 #define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
792 #define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
793 #define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
794 #define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
795 #define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
796 #define DCRN_DMASR 0x0E0 /* DMA Status Register */
803 #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
804 #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
805 #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
806 #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
839 /* System-On-Chip Version Register */
841 /* System-On-Chip Version Register (SVR) field extraction */
862 * AMCC has further subdivided the standard PowerPC 16-bit version and
1023 #define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
1197 .mask = (1 << (nc)) - 1 }
1234 /* Lazy FPU handling on uni-processor */
1242 * to match the mac we can raise this. -- Cort
1260 void *pgdir; /* root of page-table tree */
1277 (struct pt_regs *)INIT_SP - 1, /* regs */ \
1297 return (t->regs) ? t->regs->nip : 0; in thread_saved_pc()
1306 #define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
1307 #define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
1318 /* in process.c - for early bootup debug -- Cort */