include/asm/mmu.h

28 	unsigned long w:1;	/* Write-thru cache mode */
47 	unsigned long n:1;	/* No-execute */
52 /* Block Address Translation (BAT) Registers */
53 typedef struct _P601_BATU {	/* Upper part of BAT for 601 processor */
64 typedef struct _BATU {		/* Upper part of BAT (all except 601) */
76 typedef struct _P601_BATL {	/* Lower part of BAT for 601 processor */
83 typedef struct _BATL {		/* Lower part of BAT (all except 601) */
90 	unsigned long w:1;	/* Write-thru cache */
101 } BAT;  typedef
109  * Simulated two-level MMU.  This structure is used by the kernel
133 	pte	**pmap;		/* Two-level page-map structure */
152 extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
153 extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
170 #define BATL_PP_01		0x00000001 /* Read-only */
171 #define BATL_PP_10		0x00000002 /* Read-write */
178 /* BAT Block size values */
203 /* BAT Access Protection */
208 /* Macros to get values from BATs, once data is in the BAT register format */
218 	(u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4)
238  * During software tablewalk, the registers used perform mask/shift-add
368  * At present, all PowerPC 400-class processors share a similar TLB
370  * 64-entry, fully-associative TLB which is maintained totally under
372  * hardware-managed, 4-entry, fully- associative TLB which serves as a
381  * portion.  On all architectures, the data portion is 32-bits.
384  * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
389  * FSL Book-E support