Lines Matching +full:0 +full:xfffffe00
36 /* Values for PP (assumes Ks=0, Kp=1) */
37 #define PP_RWXX 0 /* Supervisor read/write, User none */
45 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
59 unsigned long ks:1; /* Supervisor key (normally 0) */
123 #define PD_MASK 0x02FF
125 #define PT_MASK 0x02FF
144 IBAT0 = 0, IBAT1, IBAT2, IBAT3,
158 #define BATU_VS 0x00000002
159 #define BATU_VP 0x00000001
160 #define BATU_INVALID 0x00000000
162 #define BATL_WRITETHROUGH 0x00000040
163 #define BATL_CACHEINHIBIT 0x00000020
164 #define BATL_MEMCOHERENCE 0x00000010
165 #define BATL_GUARDEDSTORAGE 0x00000008
166 #define BATL_NO_ACCESS 0x00000000
168 #define BATL_PP_MSK 0x00000003
169 #define BATL_PP_00 0x00000000 /* No access */
170 #define BATL_PP_01 0x00000001 /* Read-only */
171 #define BATL_PP_10 0x00000002 /* Read-write */
172 #define BATL_PP_11 0x00000003
179 #define BATU_BL_128K 0x00000000
180 #define BATU_BL_256K 0x00000004
181 #define BATU_BL_512K 0x0000000c
182 #define BATU_BL_1M 0x0000001c
183 #define BATU_BL_2M 0x0000003c
184 #define BATU_BL_4M 0x0000007c
185 #define BATU_BL_8M 0x000000fc
186 #define BATU_BL_16M 0x000001fc
187 #define BATU_BL_32M 0x000003fc
188 #define BATU_BL_64M 0x000007fc
189 #define BATU_BL_128M 0x00000ffc
190 #define BATU_BL_256M 0x00001ffc
194 #define BATU_BL_512M 0x00003ffc
195 #define BATU_BL_1G 0x00007ffc
196 #define BATU_BL_2G 0x0000fffc
197 #define BATU_BL_4G 0x0001fffc
204 #define BPP_XX 0x00 /* No access */
205 #define BPP_RX 0x01 /* Read only */
206 #define BPP_RW 0x02 /* Read/write */
209 #define BATU_VALID(x) (x & 0x3)
210 #define BATU_VADDR(x) (x & 0xfffe0000)
211 #define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \
212 | ((x & 0x0e00ULL) << 24) \
213 | ((x & 0x04ULL) << 30)))
221 #define HASH_TABLE_SIZE_64K 0x00010000
222 #define HASH_TABLE_SIZE_128K 0x00020000
223 #define HASH_TABLE_SIZE_256K 0x00040000
224 #define HASH_TABLE_SIZE_512K 0x00080000
225 #define HASH_TABLE_SIZE_1M 0x00100000
226 #define HASH_TABLE_SIZE_2M 0x00200000
227 #define HASH_TABLE_SIZE_4M 0x00400000
228 #define HASH_TABLE_MASK_64K 0x000
229 #define HASH_TABLE_MASK_128K 0x001
230 #define HASH_TABLE_MASK_256K 0x003
231 #define HASH_TABLE_MASK_512K 0x007
232 #define HASH_TABLE_MASK_1M 0x00F
233 #define HASH_TABLE_MASK_2M 0x01F
234 #define HASH_TABLE_MASK_4M 0x03F
244 #define MI_GPM 0x80000000 /* Set domain manager mode */
245 #define MI_PPM 0x40000000 /* Set subpage protection */
246 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
247 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
248 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
249 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
250 #define MI_RESETVAL 0x00000000 /* Value of register at reset */
253 * Ks = 0, Kp = 1.
256 #define MI_Ks 0x80000000 /* Should not be set */
257 #define MI_Kp 0x40000000 /* Should always be set */
264 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
265 #define MI_EVALID 0x00000200 /* Entry is valid */
266 #define MI_ASIDMASK 0x0000000f /* ASID match value */
274 #define MI_APG 0x000001e0 /* Access protection group (0) */
275 #define MI_GUARDED 0x00000010 /* Guarded storage */
276 #define MI_PSMASK 0x0000000c /* Mask of page size bits */
277 #define MI_PS8MEG 0x0000000c /* 8M page size */
278 #define MI_PS512K 0x00000004 /* 512K page size */
279 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
280 #define MI_SVALID 0x00000001 /* Segment entry is valid */
290 * pages for boot initialization. This has real page number of 0,
294 #define MI_BOOTINIT 0x000001fd
297 #define MD_GPM 0x80000000 /* Set domain manager mode */
298 #define MD_PPM 0x40000000 /* Set subpage protection */
299 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
300 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
301 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
302 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
303 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
304 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
305 #define MD_RESETVAL 0x04000000 /* Value of register at reset */
308 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
312 * Ks = 0, Kp = 1.
315 #define MD_Ks 0x80000000 /* Should not be set */
316 #define MD_Kp 0x40000000 /* Should always be set */
323 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
324 #define MD_EVALID 0x00000200 /* Entry is valid */
325 #define MD_ASIDMASK 0x0000000f /* ASID match value */
333 #define M_L1TB 0xfffff000 /* Level 1 table base address */
334 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */
343 #define MD_L2TB 0xfffff000 /* Level 2 table base address */
344 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
345 #define MD_APG 0x000001e0 /* Access protection group (0) */
346 #define MD_GUARDED 0x00000010 /* Guarded storage */
347 #define MD_PSMASK 0x0000000c /* Mask of page size bits */
348 #define MD_PS8MEG 0x0000000c /* 8M page size */
349 #define MD_PS512K 0x00000004 /* 512K page size */
350 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
351 #define MD_WT 0x00000002 /* Use writethrough page attribute */
352 #define MD_SVALID 0x00000001 /* Segment entry is valid */
392 #define MAS0_TLBSEL_MSK 0x30000000
394 #define MAS0_ESEL_MSK 0x0FFF0000
396 #define MAS0_NV(x) ((x) & 0x00000FFF)
398 #define MAS1_VALID 0x80000000
399 #define MAS1_IPROT 0x40000000
400 #define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
401 #define MAS1_TS 0x00001000
402 #define MAS1_TSIZE(x) (((x) << 7) & 0x00000F80)
405 #define MAS2_EPN 0xFFFFF000
406 #define MAS2_X0 0x00000040
407 #define MAS2_X1 0x00000020
408 #define MAS2_W 0x00000010
409 #define MAS2_I 0x00000008
410 #define MAS2_M 0x00000004
411 #define MAS2_G 0x00000002
412 #define MAS2_E 0x00000001
414 #define MAS3_RPN 0xFFFFF000
415 #define MAS3_U0 0x00000200
416 #define MAS3_U1 0x00000100
417 #define MAS3_U2 0x00000080
418 #define MAS3_U3 0x00000040
419 #define MAS3_UX 0x00000020
420 #define MAS3_SX 0x00000010
421 #define MAS3_UW 0x00000008
422 #define MAS3_SW 0x00000004
423 #define MAS3_UR 0x00000002
424 #define MAS3_SR 0x00000001
427 #define MAS4_TIDDSEL 0x000F0000
429 #define MAS4_X0D 0x00000040
430 #define MAS4_X1D 0x00000020
431 #define MAS4_WD 0x00000010
432 #define MAS4_ID 0x00000008
433 #define MAS4_MD 0x00000004
434 #define MAS4_GD 0x00000002
435 #define MAS4_ED 0x00000001
437 #define MAS6_SPID0 0x3FFF0000
438 #define MAS6_SPID1 0x00007FFE
439 #define MAS6_SAS 0x00000001
442 #define MAS7_RPN 0xFFFFFFFF
459 #define BOOKE_PAGESZ_1K 0
493 #define TLBIVAX_TLB0 0
523 { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \
524 .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \
526 .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \
543 #define LAWAR_EN 0x80000000
544 #define LAWAR_SIZE 0x0000003F
546 #define LAWAR_TRGT_IF_PCI 0x00000000
547 #define LAWAR_TRGT_IF_PCI1 0x00000000
548 #define LAWAR_TRGT_IF_PCIX 0x00000000
549 #define LAWAR_TRGT_IF_PCI2 0x00100000
550 #define LAWAR_TRGT_IF_PCIE1 0x00200000
551 #define LAWAR_TRGT_IF_PCIE2 0x00100000
552 #define LAWAR_TRGT_IF_PCIE3 0x00300000
553 #define LAWAR_TRGT_IF_LBC 0x00400000
554 #define LAWAR_TRGT_IF_CCSR 0x00800000
555 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
556 #define LAWAR_TRGT_IF_RIO 0x00c00000
557 #define LAWAR_TRGT_IF_DDR 0x00f00000
558 #define LAWAR_TRGT_IF_DDR1 0x00f00000
559 #define LAWAR_TRGT_IF_DDR2 0x01600000
561 #define LAWAR_SIZE_BASE 0xa