include/asm/immap_86xx.h

521 typedef struct ccsr_pic {  struct
522 	char	res1[64];
523 	uint	ipidr0;		/* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
524 	char	res2[12];
525 	uint	ipidr1;		/* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
526 	char	res3[12];
527 	uint	ipidr2;		/* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
528 	char	res4[12];
529 	uint	ipidr3;		/* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
530 	char	res5[12];
531 	uint	ctpr;		/* 0x40080 - Current Task Priority Register */
532 	char	res6[12];
533 	uint	whoami;		/* 0x40090 - Who Am I Register */
534 	char	res7[12];
535 	uint	iack;		/* 0x400a0 - Interrupt Acknowledge Register */
536 	char	res8[12];
537 	uint	eoi;		/* 0x400b0 - End Of Interrupt Register */
538 	char	res9[3916];
539 	uint	frr;		/* 0x41000 - Feature Reporting Register */
540 	char	res10[28];
541 	uint	gcr;		/* 0x41020 - Global Configuration Register */
544 	char	res11[92];
545 	uint	vir;		/* 0x41080 - Vendor Identification Register */
546 	char	res12[12];
547 	uint	pir;		/* 0x41090 - Processor Initialization Register */
548 	char	res13[12];
549 	uint	ipivpr0;	/* 0x410a0 - IPI Vector/Priority Register 0 */
550 	char	res14[12];
551 	uint	ipivpr1;	/* 0x410b0 - IPI Vector/Priority Register 1 */
552 	char	res15[12];
553 	uint	ipivpr2;	/* 0x410c0 - IPI Vector/Priority Register 2 */
554 	char	res16[12];
555 	uint	ipivpr3;	/* 0x410d0 - IPI Vector/Priority Register 3 */
556 	char	res17[12];
557 	uint	svr;		/* 0x410e0 - Spurious Vector Register */
558 	char	res18[12];
559 	uint	tfrr;		/* 0x410f0 - Timer Frequency Reporting Register */
560 	char	res19[12];
561 	uint	gtccr0;		/* 0x41100 - Global Timer Current Count Register 0 */
562 	char	res20[12];
563 	uint	gtbcr0;		/* 0x41110 - Global Timer Base Count Register 0 */
564 	char	res21[12];
565 	uint	gtvpr0;		/* 0x41120 - Global Timer Vector/Priority Register 0 */
566 	char	res22[12];
567 	uint	gtdr0;		/* 0x41130 - Global Timer Destination Register 0 */
568 	char	res23[12];
569 	uint	gtccr1;		/* 0x41140 - Global Timer Current Count Register 1 */
570 	char	res24[12];
571 	uint	gtbcr1;		/* 0x41150 - Global Timer Base Count Register 1 */
572 	char	res25[12];
573 	uint	gtvpr1;		/* 0x41160 - Global Timer Vector/Priority Register 1 */
574 	char	res26[12];
575 	uint	gtdr1;		/* 0x41170 - Global Timer Destination Register 1 */
576 	char	res27[12];
577 	uint	gtccr2;		/* 0x41180 - Global Timer Current Count Register 2 */
578 	char	res28[12];
579 	uint	gtbcr2;		/* 0x41190 - Global Timer Base Count Register 2 */
580 	char	res29[12];
581 	uint	gtvpr2;		/* 0x411a0 - Global Timer Vector/Priority Register 2 */
582 	char	res30[12];
583 	uint	gtdr2;		/* 0x411b0 - Global Timer Destination Register 2 */
584 	char	res31[12];
585 	uint	gtccr3;		/* 0x411c0 - Global Timer Current Count Register 3 */
586 	char	res32[12];
587 	uint	gtbcr3;		/* 0x411d0 - Global Timer Base Count Register 3 */
588 	char	res33[12];
589 	uint	gtvpr3;		/* 0x411e0 - Global Timer Vector/Priority Register 3 */
590 	char	res34[12];
591 	uint	gtdr3;		/* 0x411f0 - Global Timer Destination Register 3 */
592 	char	res35[268];
593 	uint	tcr;		/* 0x41300 - Timer Control Register */
594 	char	res36[12];
595 	uint	irqsr0;		/* 0x41310 - IRQ_OUT Summary Register 0 */
596 	char	res37[12];
597 	uint	irqsr1;		/* 0x41320 - IRQ_OUT Summary Register 1 */
598 	char	res38[12];
599 	uint	cisr0;		/* 0x41330 - Critical Interrupt Summary Register 0 */
600 	char	res39[12];
601 	uint	cisr1;		/* 0x41340 - Critical Interrupt Summary Register 1 */
602 	char	res40[12];
603 	uint	pm0mr0;		/* 0x41350 - Performance monitor 0 mask register 0  */
604 	char	res41[12];
605 	uint	pm0mr1;		/* 0x41360 - Performance monitor 0 mask register 1  */
606 	char	res42[12];
607 	uint	pm1mr0;		/* 0x41370 - Performance monitor 1 mask register 0  */
608 	char	res43[12];
609 	uint	pm1mr1;		/* 0x41380 - Performance monitor 1 mask register 1  */
610 	char	res44[12];
611 	uint	pm2mr0;		/* 0x41390 - Performance monitor 2 mask register 0  */
612 	char	res45[12];
613 	uint	pm2mr1;		/* 0x413A0 - Performance monitor 2 mask register 1  */
614 	char	res46[12];
615 	uint	pm3mr0;		/* 0x413B0 - Performance monitor 3 mask register 0  */
616 	char	res47[12];
617 	uint	pm3mr1;		/* 0x413C0 - Performance monitor 3 mask register 1  */
618 	char	res48[60];
619 	uint	msgr0;		/* 0x41400 - Message Register 0 */
620 	char	res49[12];
621 	uint	msgr1;		/* 0x41410 - Message Register 1 */
622 	char	res50[12];
623 	uint	msgr2;		/* 0x41420 - Message Register 2 */
624 	char	res51[12];
625 	uint	msgr3;		/* 0x41430 - Message Register 3 */
626 	char	res52[204];
627 	uint	mer;		/* 0x41500 - Message Enable Register */
628 	char	res53[12];
629 	uint	msr;		/* 0x41510 - Message Status Register */
630 	char	res54[60140];
631 	uint	eivpr0;		/* 0x50000 - External Interrupt Vector/Priority Register 0 */
632 	char	res55[12];
633 	uint	eidr0;		/* 0x50010 - External Interrupt Destination Register 0 */
634 	char	res56[12];
635 	uint	eivpr1;		/* 0x50020 - External Interrupt Vector/Priority Register 1 */
636 	char	res57[12];
637 	uint	eidr1;		/* 0x50030 - External Interrupt Destination Register 1 */
638 	char	res58[12];
639 	uint	eivpr2;		/* 0x50040 - External Interrupt Vector/Priority Register 2 */
640 	char	res59[12];
641 	uint	eidr2;		/* 0x50050 - External Interrupt Destination Register 2 */
642 	char	res60[12];
643 	uint	eivpr3;		/* 0x50060 - External Interrupt Vector/Priority Register 3 */
644 	char	res61[12];
645 	uint	eidr3;		/* 0x50070 - External Interrupt Destination Register 3 */
646 	char	res62[12];
647 	uint	eivpr4;		/* 0x50080 - External Interrupt Vector/Priority Register 4 */
648 	char	res63[12];
649 	uint	eidr4;		/* 0x50090 - External Interrupt Destination Register 4 */
650 	char	res64[12];
651 	uint	eivpr5;		/* 0x500a0 - External Interrupt Vector/Priority Register 5 */
652 	char	res65[12];
653 	uint	eidr5;		/* 0x500b0 - External Interrupt Destination Register 5 */
654 	char	res66[12];
655 	uint	eivpr6;		/* 0x500c0 - External Interrupt Vector/Priority Register 6 */
656 	char	res67[12];
657 	uint	eidr6;		/* 0x500d0 - External Interrupt Destination Register 6 */
658 	char	res68[12];
659 	uint	eivpr7;		/* 0x500e0 - External Interrupt Vector/Priority Register 7 */
660 	char	res69[12];
661 	uint	eidr7;		/* 0x500f0 - External Interrupt Destination Register 7 */
662 	char	res70[12];
663 	uint	eivpr8;		/* 0x50100 - External Interrupt Vector/Priority Register 8 */
664 	char	res71[12];
665 	uint	eidr8;		/* 0x50110 - External Interrupt Destination Register 8 */
666 	char	res72[12];
667 	uint	eivpr9;		/* 0x50120 - External Interrupt Vector/Priority Register 9 */
668 	char	res73[12];
669 	uint	eidr9;		/* 0x50130 - External Interrupt Destination Register 9 */
670 	char	res74[12];
671 	uint	eivpr10;	/* 0x50140 - External Interrupt Vector/Priority Register 10 */
672 	char	res75[12];
673 	uint	eidr10;		/* 0x50150 - External Interrupt Destination Register 10 */
674 	char	res76[12];
675 	uint	eivpr11;	/* 0x50160 - External Interrupt Vector/Priority Register 11 */
676 	char	res77[12];
677 	uint	eidr11;		/* 0x50170 - External Interrupt Destination Register 11 */
678 	char	res78[140];
679 	uint	iivpr0;		/* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
680 	char	res79[12];
681 	uint	iidr0;		/* 0x50210 - Internal Interrupt Destination Register 0 */
682 	char	res80[12];
683 	uint	iivpr1;		/* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
684 	char	res81[12];
685 	uint	iidr1;		/* 0x50230 - Internal Interrupt Destination Register 1 */
686 	char	res82[12];
687 	uint	iivpr2;		/* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
688 	char	res83[12];
689 	uint	iidr2;		/* 0x50250 - Internal Interrupt Destination Register 2 */
690 	char	res84[12];
691 	uint	iivpr3;		/* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
692 	char	res85[12];
693 	uint	iidr3;		/* 0x50270 - Internal Interrupt Destination Register 3 */
694 	char	res86[12];
695 	uint	iivpr4;		/* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
696 	char	res87[12];
697 	uint	iidr4;		/* 0x50290 - Internal Interrupt Destination Register 4 */
698 	char	res88[12];
699 	uint	iivpr5;		/* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
700 	char	res89[12];
701 	uint	iidr5;		/* 0x502b0 - Internal Interrupt Destination Register 5 */
702 	char	res90[12];
703 	uint	iivpr6;		/* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
704 	char	res91[12];
705 	uint	iidr6;		/* 0x502d0 - Internal Interrupt Destination Register 6 */
706 	char	res92[12];
707 	uint	iivpr7;		/* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
708 	char	res93[12];
709 	uint	iidr7;		/* 0x502f0 - Internal Interrupt Destination Register 7 */
710 	char	res94[12];
711 	uint	iivpr8;		/* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
712 	char	res95[12];
713 	uint	iidr8;		/* 0x50310 - Internal Interrupt Destination Register 8 */
714 	char	res96[12];
715 	uint	iivpr9;		/* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
716 	char	res97[12];
717 	uint	iidr9;		/* 0x50330 - Internal Interrupt Destination Register 9 */
718 	char	res98[12];
719 	uint	iivpr10;	/* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
720 	char	res99[12];
721 	uint	iidr10;		/* 0x50350 - Internal Interrupt Destination Register 10 */
722 	char	res100[12];
723 	uint	iivpr11;	/* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
724 	char	res101[12];
725 	uint	iidr11;		/* 0x50370 - Internal Interrupt Destination Register 11 */
726 	char	res102[12];
727 	uint	iivpr12;	/* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
728 	char	res103[12];
729 	uint	iidr12;		/* 0x50390 - Internal Interrupt Destination Register 12 */
730 	char	res104[12];
731 	uint	iivpr13;	/* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
732 	char	res105[12];
733 	uint	iidr13;		/* 0x503b0 - Internal Interrupt Destination Register 13 */
734 	char	res106[12];
735 	uint	iivpr14;	/* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
736 	char	res107[12];
737 	uint	iidr14;		/* 0x503d0 - Internal Interrupt Destination Register 14 */
738 	char	res108[12];
739 	uint	iivpr15;	/* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
740 	char	res109[12];
741 	uint	iidr15;		/* 0x503f0 - Internal Interrupt Destination Register 15 */
742 	char	res110[12];
743 	uint	iivpr16;	/* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
744 	char	res111[12];
745 	uint	iidr16;		/* 0x50410 - Internal Interrupt Destination Register 16 */
746 	char	res112[12];
747 	uint	iivpr17;	/* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
748 	char	res113[12];
749 	uint	iidr17;		/* 0x50430 - Internal Interrupt Destination Register 17 */
750 	char	res114[12];
751 	uint	iivpr18;	/* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
752 	char	res115[12];
753 	uint	iidr18;		/* 0x50450 - Internal Interrupt Destination Register 18 */
754 	char	res116[12];
755 	uint	iivpr19;	/* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
756 	char	res117[12];
757 	uint	iidr19;		/* 0x50470 - Internal Interrupt Destination Register 19 */
758 	char	res118[12];
759 	uint	iivpr20;	/* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
760 	char	res119[12];
761 	uint	iidr20;		/* 0x50490 - Internal Interrupt Destination Register 20 */
762 	char	res120[12];
763 	uint	iivpr21;	/* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
764 	char	res121[12];
765 	uint	iidr21;		/* 0x504b0 - Internal Interrupt Destination Register 21 */
766 	char	res122[12];
767 	uint	iivpr22;	/* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
768 	char	res123[12];
769 	uint	iidr22;		/* 0x504d0 - Internal Interrupt Destination Register 22 */
770 	char	res124[12];
771 	uint	iivpr23;	/* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
772 	char	res125[12];
773 	uint	iidr23;		/* 0x504f0 - Internal Interrupt Destination Register 23 */
774 	char	res126[12];
775 	uint	iivpr24;	/* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
776 	char	res127[12];
777 	uint	iidr24;		/* 0x50510 - Internal Interrupt Destination Register 24 */
778 	char	res128[12];
779 	uint	iivpr25;	/* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
780 	char	res129[12];
781 	uint	iidr25;		/* 0x50530 - Internal Interrupt Destination Register 25 */
782 	char	res130[12];
783 	uint	iivpr26;	/* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
784 	char	res131[12];
785 	uint	iidr26;		/* 0x50550 - Internal Interrupt Destination Register 26 */
786 	char	res132[12];
787 	uint	iivpr27;	/* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
788 	char	res133[12];
789 	uint	iidr27;		/* 0x50570 - Internal Interrupt Destination Register 27 */
790 	char	res134[12];
791 	uint	iivpr28;	/* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
792 	char	res135[12];
793 	uint	iidr28;		/* 0x50590 - Internal Interrupt Destination Register 28 */
794 	char	res136[12];
795 	uint	iivpr29;	/* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
796 	char	res137[12];
797 	uint	iidr29;		/* 0x505b0 - Internal Interrupt Destination Register 29 */
798 	char	res138[12];
799 	uint	iivpr30;	/* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
800 	char	res139[12];
801 	uint	iidr30;		/* 0x505d0 - Internal Interrupt Destination Register 30 */
802 	char	res140[12];
803 	uint	iivpr31;	/* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
804 	char	res141[12];
805 	uint	iidr31;		/* 0x505f0 - Internal Interrupt Destination Register 31 */
806 	char	res142[4108];
807 	uint	mivpr0;		/* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
808 	char	res143[12];
809 	uint	midr0;		/* 0x51610 - Messaging Interrupt Destination Register 0 */
810 	char	res144[12];
811 	uint	mivpr1;		/* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
812 	char	res145[12];
813 	uint	midr1;		/* 0x51630 - Messaging Interrupt Destination Register 1 */
814 	char	res146[12];
815 	uint	mivpr2;		/* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
839 } ccsr_pic_t;  argument